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RC5050
PRODUCT SPECIFICATION
12
Figure 5. R
DS,ON
vs. V
GS
for Selected MOSFETs
Converter Efficiency
Losses due to parasitic resistance in the switches, inductor
coil and sense resistor dominate at high load current levels.
The major loss mechanisms under heavy loads, in usual
order of importance, are:
MOSFET I
2
R losses
Inductor coil losses
Sense resistor losses
Gate-charge losses
Diode-conduction losses
Transition losses
Input capacitor losses
Losses due to the operating supply current of the IC.
The following sections provide details of these dominant
loss components.
Selecting the Inductor
The inductor is one of the most critical components to be
selected in the DC-DC converter application.. The critical
parameters are inductance (L), maximum DC current (Io)
and the DC coil resistance (R
l
). The inductor core material
is a crucial factor in determining the amount of current the
inductor will be able to withstand. As with all engineering
designs, tradeoffs exist between various types of core materi-
als. In general, Ferrites are popular due to their low cost, low
EMI properties and high frequency (>500KHz) characteris-
tics. Molypermalloy powder (MPP) materials exhibit good
saturation characteristics, low EMI and low hysteresis
losses; however, they tend to be expensive and more effec-
tively utilized at operating frequencies below 400KHz.
Another critical parameter is the DC winding resistance of
the inductor. This value should typically be reduced as much
as possible, as the power loss in the DC resistance will
degrade the efficiency of the converter by the relationship:
P
LOSS
= I
O
2
x R
l
.
Choosing the value of the inductor is a tradeoff between
allowable ripple voltage and required transient response. The
system designer can choose any value within the allowed
range in order to maximize either ripple or transient perfor-
mance. The first order equation (close approximation) for
minimum inductance is:
V
V
–
(
)
f
V
IN
where:
V
IN
= Input Power Supply
V
OUT
= Output Voltage
f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors
in parallel
V
r
= Peak to peak output ripple voltage budget.
The first order equation for maximum allowed inductance is:
V
V
–
(
I
p
2
where:
Co = The total output capacitance
I
p
= Peak to peak load transient current
V
tb
= The output voltage tolerance budget allocated to
load transient
D
m
= Maximum duty cycle for the DC/DC converter
(usually 95%).
Some margin should be maintained between L
min
and L
max
.
Adding margin by increasing L
max
almost always adds
expense since all the variables are predetermined by system
performance except for C
o
, which must be increased to
increase L
max
. Adding margin by decreasing L
min
can either
be done by purchasing capacitors with lower ESR or by
increasing the DC/DC converter switching frequency. The
RC5050 is capable of running at high switching frequencies
and provides significant cost savings for the newer CPU
systems that typically run at high supply current.
Implementing Short Circuit Protection
Intel currently requires all power supply manufacturers to
provide continuous protection against short circuit condi-
tions that may damage the CPU. To address this requirement,
Fairchild Semiconductor has implemented a current sense
methodology to limit the power delivered to the load in the
event of an overcurrent condition. The voltage drop created
by the output current flowing across a sense resistor is pre-
sented to one terminal of an internal comparator with hys-
terisis. The other comparator terminal has a threshold
voltage, nominally 120mV. Table 6 states the limits for the
comparator threshold of the Switching Regulator.
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
1.5 2
2.5 3
Gate-Source Voltage, V
GS
(V)
3.5 4
5
6
7
8
9
10 11
R
D
W
)
Fuji
Fuji
706A
706AEL
L
min
-----------------------------------
OUT
V
V
r
ESR
′
′
=
L
min
2Co
m
V
tb
------------------------------------D
′
=