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參數(shù)資料
| 型號(hào)： | RC7105 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | RC71 SERIES, LOW SKEW CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大小： | 83K |
| 代理商： | RC7105 |
RC7105
PRODUCT SPECIFICATION
8
Advanced
Infor
mation
Table 2. Data Bytes 0-2 Serial Configuration Map
Note:
At power up all SDRAM outputs are enabled and active. Program all reserved bits to a”0”.
Bit(s)
Affected Pin
Bit Control
Pin No.
Pin Name
Control Function
0
1
Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
11
SDRAM5
Clock Output Disable
Low
Active
6
10
SDRAM4
Clock Output Disable
Low
Active
5
N/A
Reserved
(Reserved)
—
4
N/A
Reserved
(Reserved)
—
3
7
SDRAM3
Clock Output Disable
Low
Active
2
6
SDRAM2
Clock Output Disable
Low
Active
1
3
SDRAM1
Clock Output Disable
Low
Active
0
2
SDRAM0
Clock Output Disable
Low
Active
Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
27
SDRAM11
Clock Output Disable
Low
Active
6
26
SDRAM10
Clock Output Disable
Low
Active
5
23
SDRAM9
Clock Output Disable
Low
Active
4
22
SDRAM8
Clock Output Disable
Low
Active
3
N/A
Reserved
(Reserved)
—
2
N/A
Reserved
(Reserved)
—
1
19
SDRAM7
Clock Output Disable
Low
Active
0
18
SDRAM6
Clock Output Disable
Low
Active
Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
N/A
Reserved
(Reserved)
—
6
12
SDRAM12
Clock Output Disable
Low
Active
5
N/A
Reserved
(Reserved)
—
4
N/A
Reserved
(Reserved)
—
3
N/A
Reserved
(Reserved)
—
2
N/A
Reserved
(Reserved)
—
1
N/A
Reserved
(Reserved)
—
0
N/A
Reserved
(Reserved)
—
Writing Data Bytes
Each bit of the 10 data bytes controls a particular device
function within the RC7105. Bit 7, the MSB, is written rst.
See Table 2 for bit descriptions of Data Bytes 0–2.
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