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參數(shù)資料
| 型號： | RC7105 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | RC71 SERIES, LOW SKEW CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 83K |
| 代理商： | RC7105 |
PRODUCT SPECIFICATION
RC7105
5
Advanced
Infor
mation
How To Use the Serial Data Interface
Electrical Requirements
Figure 1 shows the architecture for the I2C serial interface bus
used with the RC7105. Devices on the bus signal with an open
drain logic output that actively pulls the bus line low, or lets
the bus default to VDD (logic 1). The pull-up resistor on each
bus line, SCL and SDA, establishes a default logic 1.
Although the RC7105 is a slave device which cannot write
data on the bus, it does transmit an “acknowledge” data pulse
after each byte is received. Thus, the SDA line is an I/O pin.
The pull-up resistor value should be designed to meet the rise
and fall times specied in AC parameters, based on total bus
line capacitance.
Signaling Requirements
As demonstrated in Figure 2, the I2C protocol denes valid
data bits as stable logic 0 or 1 condition on the SDA line
during an SCL high (logic 1) pulse. A transitioning SDA line
during an SCL high pulse may be read as a start or stop
pulse.
Figure 3 shows how a “start bit” commands the beginning
of a write sequence. The “stop bit” shown signies that the
sequence has ended. The RC7105 sends an “acknowledge”
pulse after receiving eight data bits by asserting a low pulse
on SDA, as shown in Figure 4.
Figure 2. Serial Data Bus Valid Data Bit
Figure 3. Serial Data Bus Start and Stop Bit
SDA
SCL
VALID
DATA
BIT
CHANGE
OF DATA
ALLOWED
SDA
SCL
START
BIT
STOP
BIT
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