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參數(shù)資料
| 型號： | RC7105 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | RC71 SERIES, LOW SKEW CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 83K |
| 代理商： | RC7105 |
PRODUCT SPECIFICATION
RC7105
7
Advanced
Infor
mation
Functional Description
Output Drivers
The RC7105 uses CMOS type output buffers which drive
the output rail-to-rail (GND to VDD) into typical capacitive
loads. Because of this the outputs are both TTL and CMOS
level compatible. Nominal output buffer impedance is 15
.
Operation
The RC7105 is programmed by writing ten bytes of eight
bits each. See Table 1 for byte sequence.
Table 1. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the RC7105 to accept the bits in Data Bytes 0-6 for
internal register configuration. Since other devices may exist on
the same common serial data bus, it is necessary to have a
specific slave address for each potential receiver. The slave
receiver address for the RC7105 is 11010010. Register setting
will not be made if the Slave Address is not correct (or is for an
alternate slave receiver).
2
Command
Code
Don’t Care
Unused by the RC7105, therefore bit values are ignored (don’t
care). This byte must be included in the data write sequence to
maintain proper byte allocation. The Command Code Byte is
part of the standard serial communication protocol and may be
used when writing ot another addressed slave receiver on the
serial data bus.
3
Byte Count
Don’t Care
Unused by the RC7105, therefore bit values are ignored (don’ t
care). This byte must be included in the data write sequence to
maintain proper byte allocation. The Byte Count Byte is part of
the standard serial communication protocol and may be used
when writing to another addressed slave receiver on the serial
data bus.
4
Data Byte 0
Refer to Table 2
The data bits in these bytes set internal RC7105 registers that
control device operation. The data bits are only accepted when
the Address Byte bit sequence is 11010010, as noted above.
For description of bit control functions, refer to Table 2, Data
Byte Serial Configuration Map.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
Don’t Care
Refer to Fairchild clock drivers.
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
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