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參數(shù)資料
| 型號： | RC5061M |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Current-Mode SMPS Controller |
| 中文描述： | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 135K |
| 代理商： | RC5061M |
PRODUCT SPECIFICATION
RC5061
REV. 1.0.0 7/6/00
3
Absolute Maximum Ratings
Note:
1. Component mounted on demo board in free air.
Recommended Operating Conditions
Supply Voltage VCCA to GND
Supply Voltage VCCP to GND
Voltage Identification Code Inputs, VID0-VID4
All Other Pins
Junction Temperature, T
Storage Temperature
Lead Soldering Temperature, 10 seconds
Thermal Resistance Junction-to-ambient,
13.5V
15V
VCCA
13.5V
150°C
J
-65 to 150°C
300°C
75°C/W
Θ
JA1
Parameter
Supply Voltage VCCA
Input Logic HIGH
Input Logic LOW
Ambient Operating Temperature
Output Driver Supply, VCCP
Conditions
Min.
4.5
2.0
Typ.
5
Max.
5.25
Units
V
V
V
°C
V
0.8
70
13.2
0
10.8
12
Electrical Specifications
(V
CCA
= 5V, V
CCP
= 12V, V
The denotes specifications which apply over the full operating temperature range.
OUT
= 2.0V, and T
A
= +25°C using circuit in Figure 1 unless otherwise noted.)
Parameter
VCC Regulator
Output Voltage
Output Current
Initial Voltage Setpoint
Conditions
Min.
Typ.
Max.
Units
See Table 1
1.3
3.5
V
A
V
V
V
18
I
LOAD
= 0.8A, V
OUT
OUT
OUT
= 2.400V
= 2.000V
= 1.550V
= 2.000V
OUT
= 1.550V
V
V
2.397
2.000
1.550
2.424
2.020
1.565
+8
+6
-4
14.4
60
11
2.454
2.040
1.580
Output Temperature Drift
T
A
= 0 to 70°C, V
OUT
V
mV
mV
mV/V
K
mV
mVpk
V
Line Regulation
Internal Droop Impedance
Maximum Droop
Output Ripple
Total Output Variation,
Steady State
Total Output Variation,
Transient
Short Circuit Detect Current
Efficiency
Output Driver Rise & Fall
Time
Output Driver Deadtime
V
I
LOAD
IN
= 4.75V to 5.25V
= 0.8A to 12.5A
13.0
15.8
20MHz BW, I
V
OUT
= 2.000V
V
OUT
= 1.550V
I
LOAD
= 0.8A to 18A, V
LOAD
= 18A
1
3
1.940
1.480
1.900
1.480
45
2.070
1.590
2.100
1.590
60
2
OUT
OUT
= 2.000V
= 1.550V
V
3
V
50
85
50
μA
%
nsec
I
See Figure 3
LOAD
= 18A, V
OUT
= 2.0V
See Figure 3
50
nsec
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