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型號：	RC5053
文件頁數(shù)：	945/1328頁
文件大?。?/td>	9519K
代理商：	RC5053

PRODUCT SPECIFICATION

Functional Description

The block diagram of the RC6516 consists of three general

IF amplifiers with gain control

Synchronous demodulator

Frequency phase lock loop (FPLL) and auxiliary circuits

The IF Section

There are two IF amplifiers capacitatively coupled to each

other and the subsequent stages. The first amplifier has a

maximum gain of 24dB and an AGC range of more than

14dB. The second amplifier has a maximum gain of 16dB

and gain reduction capability of 30dB. To minimize the

Noise Figure degradation with gain reduction the second

stage fully gain reduces before the first stage gain reduces.

The transition point is set by the voltage on the DLYADJ pin.

The voltage on CAGC pin directly determines the gain of the

two IF stages. When the voltage on CAGC is lower the IF

gain is lower. When the CGAC voltage is higher than the

DLYADJ the gain reduction is primarily in the second stage.

When the CAGC voltage is lower than DLYADJ, only the

first stage gain is reduced at a much slower rate. The tuner

AGC control voltage TAGC also changes this range to gain

reduce the external tuner. This avoids the amplifiers from

being overdriven into distortion. During AFC defeat mode

these IF amplifiers are disabled with more than 50dB of sig-

nal isolation.

Gain Control

The gain control signal is developed on the capacitor at the

CAGC pin, by charge pump and AGC control circuits. TTL/

CMOS signals on the G

pins build the voltage

through the charge pump current at CAGC pin. Continuous

pulses on GUP pin increases the CAGC voltage and pulses

on the GDN pin reduces the CAGC voltage. Table 1 shows

the truth table for gain control.

Synchronous Demodulator

This section consists of In-phase (I) and Quadrature (Q)

multipliers/mixers.

During normal operation the incoming signal processed by

the two IF stages is capacitatively coupled to the linear (RF)

port of both the mixers. The signals for the LO port of the I

& Q mixers come from the FPLL section. The switching sig-

nals are in quadrature and phase locked to a small pilot

present in the IF signal. The signal levels for this multiplying

port use limiting amplitudes. The I channel output is then fil-

tered to reject the high frequency components while not dis-

torting the video band signals. The filtered output is also

amplified to cover the full range of A/D converter that fol-

lows. The Q channel signal is used by the FPLL section

described below.

The FPLL Section

The FPLL consists of a VCO working at 4 times the pilot fre-

quency. The frequency is set by external LC components and

also controlled with a varactor. This VCO signal is passed

through a divide by 4 prescaler to provide two signals in

quadrature at the frequency of the pilot. These signals are

used by the I & Q multipliers. The VCO is frequency and

phase locked to the 4x pilot frequency which is typically

46.69MHz. The VCO thus operates at 186.7MHz in a typical

16 VSB decoder. Frequency acquisition is possible by means

of the third multiplier on chip and AFC filter off-chip. The

PLL circuit is formed by the Q channel mixer, third

multiplier-charge pump, external PLL filter and the VCO.

Due to component variations, the VCO frequency may not be

within the pull in range of the FPLL. The AFCSW signal is

used for activating this start up calibration. An auxiliary

crystal oscillator signal at the pilot frequency of 46.6MHz is

injected into the input port of the mixers, to pull the VCO to

the desired frequency during the start up mode. During this

mode the XTAL oscillator and the I-channel charge pump

are activated and the IF gain stages are disabled. There is

also the shutdown mode during which the VCO, the crystal

oscillator and the tuner control are disabled. These various

states are determined as shown in Table 1.

Table 1. Truth Table for Digital Circuitry

otherwise specified

No Gain Change (over

symbol period)

Increase Gain

Decrease Gain

Crystal is OFF, VCO is ON

Crystal is OFF, VCO is

OFF, Tuner AGC is Hi-Z

Crystal is ON, VCO is on,

I-channel Charge Pump is

ON for acquisition

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
RC5053B WAF	制造商:Fairchild Semiconductor Corporation 功能描述:
RC5053F	制造商:未知廠家制造商全稱:未知廠家功能描述:Voltage-Mode SMPS Controller
RC5053G	制造商:未知廠家制造商全稱:未知廠家功能描述:Voltage-Mode SMPS Controller
RC5053M	制造商:Fairchild Semiconductor Corporation 功能描述:SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO20
RC5053MSA	制造商:Freescale Semiconductor 功能描述:5053MSA

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