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參數(shù)資料
| 型號： | RC32434-350BC |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDT TInterprise Integrated Communications Processor |
| 中文描述： | IDT公司TInterprise集成通信處理器 |
| 文件頁數(shù)： | 22/53頁 |
| 文件大?。?/td> | 444K |
| 代理商： | RC32434-350BC |
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22 of 53
January 19, 2006
IDT RC32434
MDATA[7:0]
Tsu_8c
EXTCLK rising
6.0
—
6.0
—
6.0
—
6.0
—
ns
See Figures 8
and 9 (cont.).
Thld_8c
0
—
0
—
0
—
0
—
ns
Tdo_8c
0.4
4.5
0.4
4.5
0.4
4.5
0.4
4.5
ns
Tdz_8c
2
0
0.5
0
0.5
0
0.5
0
0.5
ns
Tzd_8c
2
0.4
3.3
0.4
3.3
0.4
3.3
0.4
3.3
ns
EXTCLK
3
Tper_8d
none
7.5
—
6.66
—
6.66
—
6.66
—
ns
BDIRN
Tdo_8e
EXTCLK rising
0.4
3.8
0.4
3.8
0.4
3.8
0.4
3.8
ns
Tdz_8e
2
—
—
—
—
—
—
—
—
ns
Tzd_8e
2
—
—
—
—
—
—
—
—
ns
BOEN
Tdo_8f
EXTCLK rising
0.4
3.8
0.4
3.8
0.4
3.8
0.4
3.8
ns
Tdz_8f
2
—
—
—
—
—
—
—
—
ns
Tzd_8f
2
—
—
—
—
—
—
—
—
ns
WAITACKN
4
Tsu_8h
EXTCLK rising
6.5
—
6.5
—
6.5
—
6.5
—
ns
Thld_8h
0
—
0
—
0
—
0
—
ns
Tpw_8h
2
none
2(EXTCLK)
—
2(EXTCLK)
—
2(EXTCLK)
—
2(EXTCLK)
—
ns
CSN[3:0]
Tdo_8i
EXTCLK rising
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
ns
Tdz_8i
2
—
—
—
—
—
—
—
—
ns
Tzd_8i
2
—
—
—
—
—
—
—
—
ns
RWN
Tdo_8j
EXTCLK rising
0.4
3.8
0.4
3.8
0.4
3.8
0.4
3.8
ns
Tdz_8j
2
—
—
—
—
—
—
—
—
ns
Tzd_8j
2
—
—
—
—
—
—
—
—
ns
OEN
Tdo_8k
EXTCLK rising
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
ns
Tdz_8k
2
—
—
—
—
—
—
—
—
ns
Tzd_8k
2
—
—
—
—
—
—
—
—
ns
WEN
Tdo_8l
EXTCLK rising
0.4
3.7
0.4
3.7
0.4
3.7
0.4
3.7
ns
Tdz_8l
2
—
—
—
—
—
—
—
—
ns
Tzd_8l
2
—
—
—
—
—
—
—
—
ns
1.
The RC32434 provides bus turnaround cycles to prevent bus contention when going fromread to write, write to read, and during external bus ownership. For example, there are no
cycles where an external device and the RC32434 are both driving. See Chapter 6, Device Controller, in the RC32434 User Reference Manual.
2.
The values for this symbol were determned by calculation, not by testing.
3.
The frequency of EXTCLK is programmable. See the External Clock Divider (MDATA[5:4]) description in Table 3 of this data sheet.
4.
WAITACKN must meet the setup and hold times if it is synchronous or the mnimumpulse width if it is asynchronous.
S ignal
S ymbol
Referenc e
Edge
266MHz
300MHz
350MHz
400MHz
Unit
Condi-
tions
T iming
Diagram
Referenc e
Mn
Max
Mn
Max
Min
Max
Mn
Max
Table 8 Memory and Peripheral Bus AC Timing Characteristics (Part 2 of 2)
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| RC32434-350BCI | IDT TInterprise Integrated Communications Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RC32434-350BCI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT TInterprise Integrated Communications Processor |
| RC32434-400BC | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT TInterprise Integrated Communications Processor |
| RC32434-400BCI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT TInterprise Integrated Communications Processor |
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