參數(shù)資料
型號: RC32434-350BC
廠商: Integrated Device Technology, Inc.
英文描述: IDT TInterprise Integrated Communications Processor
中文描述: IDT公司TInterprise集成通信處理器
文件頁數(shù): 21/53頁
文件大小: 444K
代理商: RC32434-350BC
21 of 53
January 19, 2006
IDT RC32434
Figure 7 DDR SDRAMTiming Waveform —Write Access
S ignal
S ymbol
Referenc e
Edge
266MHz
300MHz
350MHz
400MHz
Unit
Condi-
tions
T iming
Diagram
Referenc e
Mn
Max
Mn
Max
Min
Max
Mn
Max
Memory and Peripheral Bus
1
See Figures 8
and 9.
MADDR[21:0]
Tdo_8a
EXTCLK rising
0.4
4.5
0.4
4.5
0.4
4.5
0.4
4.5
ns
Tdz_8a
2
ns
Tzd_8a
2
ns
MADDR[25:22]
Tdo_8b
EXTCLK rising
0.4
4.5
0.4
4.5
0.4
4.5
0.4
4.5
ns
Tdz_8b
2
ns
Tzd_8b
2
ns
Table 8 Memory and Peripheral Bus AC Timing Characteristics (Part 1 of 2)
2
DDRDATA is either 32-bits or 16-bits wide depending on the DBW control bit in DDRC Register
(see
Chapter 7, DDR Controller, in the RC32434 User Reference Manual
).
RowA
Col A0
Col A2
NOP
ACTV
NOP
WR
WR
NOP
NOP
NOP
NOP
NOP
BNKx
BNKx
FF
DM0 DM1
DM3
FF
D0
D1 D2
D3
Tdo_7k
Tdo_7k
Tdo_7l
Tdo_7l
Tdo_7m
Tdo_7m
Tdo_7m
Tdo_7m
DDRCKP
DDRCKN
DDRCSN
DDRADDR[13:0]
DDRCMD
1
DDRCKE
DDRBA[1:0]
DDRDQSx
DDRDM[1:0]
DDRDATA[15:0]
2
DM2
1
DDRCMD contains DDRRASN, DDRCASN and DDRWEN.
DDRDQSx
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