參數(shù)資料
型號: R5F562N8ADLE#U0
廠商: Renesas Electronics America
文件頁數(shù): 83/148頁
文件大?。?/td> 0K
描述: MCU 32BIT FLASH 512KROM 145TFLGA
產(chǎn)品培訓(xùn)模塊: RX Compare Match Timer
RX DMAC
標(biāo)準(zhǔn)包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: EBI/EMI,I²C,SCI,SPI,USB
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 103
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10/12b,D/A 2x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 145-TFLGA
包裝: 托盤
R01DS0052EJ0130 Rev.1.30
Page 4 of 147
2012.01.11
RX62N Group, RX621 Group
1. Overview
Timers
Programmable pulse
generator
(4 bits x 4 groups) x 2 units
Pulse output with the MTU output as a trigger
Maximum of 32-bit pulse output possible
8-bit timers
(8 bits x 2 channels) x 2 units
Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5 and SCI6
Compare match
timer
(16 bits x 2 channels) x 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Watchdog timer
8 bits x 1 channel
Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128,
PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072)
Switchable between watchdog timer mode and interval timer mode
Independent
watchdog timer
14 bits x 1 channel
Counter-input clock: Dedicated on-chip oscillator
Realtime clock
Clock source: Subclock
Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Communication
function
Ethernet controller
Input and output of Ethernet/IEEE 802.3 frames
Transfer at 10 or 100 Mbps
Full- and half-duplex modes
MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
Detection of Magic PacketsTM* or output of a "wake-on-LAN" signal (WOL)
Compliance with flow control as defined in IEEE 802.3x standards
Note: * Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.
DMA controller for
Ethernet controller
Alleviation of CPU loads by the descriptor control method
Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes
USB 2.0 host/
function module
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Single port (176-pin products: two ports)
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus power are selectable
OTG (On the Go) operation is possible
Incorporates 2 Kbytes of RAM as a transfer buffer
Serial
communications
interfaces
6 channels
Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
Multi-processor communications function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5 and SCI6
Table 1.1
Outline of Specifications (3 / 4)
Classification
Module/Function
Description
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