參數(shù)資料
型號: R5F562N8ADLE#U0
廠商: Renesas Electronics America
文件頁數(shù): 142/148頁
文件大小: 0K
描述: MCU 32BIT FLASH 512KROM 145TFLGA
產(chǎn)品培訓(xùn)模塊: RX Compare Match Timer
RX DMAC
標準包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: EBI/EMI,I²C,SCI,SPI,USB
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 103
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10/12b,D/A 2x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 145-TFLGA
包裝: 托盤
2004 Microchip Technology Inc.
DS39609B-page 91
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-3:
INTCON3 REGISTER
R/W-1
R/W-0
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
bit 7
bit 0
bit 7
INT2IP: INT2 External Interrupt Priority bit
1
= High priority
0
= Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1
= High priority
0
= Low priority
bit 5
INT3IE: INT3 External Interrupt Enable bit
1
= Enables the INT3 external interrupt
0
= Disables the INT3 external interrupt
bit 4
INT2IE: INT2 External Interrupt Enable bit
1
= Enables the INT2 external interrupt
0
= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1
= Enables the INT1 external interrupt
0
= Disables the INT1 external interrupt
bit 2
INT3IF: INT3 External Interrupt Flag bit
1
= The INT3 external interrupt occurred (must be cleared in software)
0
= The INT3 external interrupt did not occur
bit 1
INT2IF: INT2 External Interrupt Flag bit
1
= The INT2 external interrupt occurred (must be cleared in software)
0
= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1
= The INT1 external interrupt occurred (must be cleared in software)
0
= The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
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