參數資料
型號: R5F562N8ADFB#V0
廠商: Renesas Electronics America
文件頁數: 61/148頁
文件大?。?/td> 0K
描述: MCU 32BIT FLASH 512KROM 144LQFP
產品培訓模塊: RX Compare Match Timer
RX DMAC
標準包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: EBI/EMI,I²C,SCI,SPI,USB
外圍設備: DMA,LVD,POR,PWM,WDT
輸入/輸出數: 103
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數據轉換器: A/D 8x10/12b,D/A 2x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
R01DS0052EJ0130 Rev.1.30
Page 2 of 147
2012.01.11
RX62N Group, RX621 Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products.
Table 1.1
Outline of Specifications (1 / 4)
Classification
Module/Function
Description
CPU
Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 x 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
Memory-protection unit (MPU)
FPU
Single precision (32-bit) floating point
Data types and floating-point exceptions in conformance with the IEEE754 standard
Memory
ROM
ROM capacity: 512 Kbytes (max.)
Two on-board programming modes
Boot mode (The user MAT is programmable via the SCI and USB.)
User program mode
Parallel programmer mode (for off-board programming)
RAM
RAM capacity: 96 Kbytes (max.)
Data flash
Data flash capacity: 32 Kbytes
MCU operating modes
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled
expansion mode (software switching)
Clock
Clock generation
circuit
Two circuits: Main clock oscillator and subclock oscillator
Internal oscillator: Low-speed on-chip oscillator
Structure of a PLL frequency synthesizer and frequency divider for selectable operating
frequency
Oscillation stoppage detection
Independent frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system
clock (ICLK): 8 to 100 MHz
Peripheral modules run in synchronization with the peripheral module
clock (PCLK): 8 to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK pin): 8 to 50 MHz*1
Reset
Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent
watchdog timer reset, and deep software standby reset
Voltage detection circuit
When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset
or internal interrupt is generated.
Low power
consumption
Low power
consumption
facilities
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
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