參數(shù)資料
型號： R5F562N8ADFB#V0
廠商： Renesas Electronics America
文件頁數(shù)： 51/148頁
文件大小： 0K
描述： MCU 32BIT FLASH 512KROM 144LQFP
產(chǎn)品培訓(xùn)模塊： RX Compare Match Timer
RX DMAC
標準包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： EBI/EMI，I²C，SCI，SPI，USB
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 103
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 2x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
包裝： 托盤
2004 Microchip Technology Inc.
DS39609B-page 143
PIC18F6520/8520/6620/8620/6720/8720
14.0
TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
16-bit timer/counter
(two 8-bit registers; TMR3H and TMR3L)
Readable and writable (both registers)
Internal or external clock select
Interrupt-on-overflow from FFFFh to 0000h
Reset from CCP module trigger
Figure 14-1 is a simplified block diagram of the Timer3
module.
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN), which can be a clock source for
Timer3.
REGISTER 14-1:
T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1
= Enables register read/write of Timer3 in one 16-bit operation
0
= Enables register read/write of Timer3 in two 8-bit operations
bit 6, 3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
11
= Timer3 and Timer4 are the clock sources for CCP1 through CCP5
10
= Timer3 and Timer4 are the clock sources for CCP3 through CCP5;
Timer1 and Timer2 are the clock sources for CCP1 and CCP2
01
= Timer3 and Timer4 are the clock sources for CCP2 through CCP5;
Timer1 and Timer2 are the clock sources for CCP1
00
= Timer1 and Timer2 are the clock sources for CCP1 through CCP5
bit 5-4
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11
= 1:8 Prescale value
10
= 1:4 Prescale value
01
= 1:2 Prescale value
00
= 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1
= Do not synchronize external clock input
0
= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
TMR3CS: Timer3 Clock Source Select bit
1
= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the
first falling edge)
0
= Internal clock (FOSC/4)
bit 0
TMR3ON: Timer3 On bit
1
= Enables Timer3
0
= Stops Timer3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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