參數(shù)資料
型號(hào)： R2033K-E2
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： 3 wire interface Real-Time Clock ICs
中文描述： 0 TIMER(S), REAL TIME CLOCK, QCC12
封裝： 2 X 2 MM, 1 MM HEIGHT, FFP-12
文件頁(yè)數(shù)： 38/50頁(yè)
文件大?。?/td> 542K
代理商： R2033K-E2
R2033K/T
Alarm and Periodic Interrupt
38
The R2033K/T incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to
generate alarm signals and periodic interrupt signals for output from the INTR pin as described below.
(1) Alarm Interrupt Circuit
The alarm interrupt circuit is configured to generate alarm signals for output from the INTR , which is driven low
(enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week,
hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the
day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit
settings).
(2) Periodic Interrupt Circuit
The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in
the level mode for output from the INTR pin depending on the CT2, CT1, and CT0 bit settings in the control
register 1.
The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in
the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0
bits in the Control Register 1) as listed in the table below.
Flag bits
Alarm_W
WAFG
(D1 at Address Fh)
(D7 at Address Eh)
Alarm_D
DAFG
(D0 at Address Fh)
(D6 at Address Eh)
Peridic interrupt
CTFG
(D2 at Address Fh)
(These bit setting of “0” disable the Periodic Interrupt)
(D2 to D0 at Address Eh)
* At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1,
the INTR pin is driven high (disabled).
* When two types of interrupt signals are output simultaneously from the INTR pin, the output from the
INTR pin becomes an OR waveform of their negative logic.
Enable bits
WALE
DALE
CT2=CT1=CT0=0
In this event, which type of interrupt signal is output from the INTR pin can be confirmed by reading the
DAFG, and CTFG bit settings in the Control Register 2.
Example: Combined Output to INTR Pin Under Control of
Alarm_D and Periodic Interrupt
Periodic Interrupt
INTR
Alarm_D
相關(guān)PDF資料
PDF描述
R2033T 3 wire interface Real-Time Clock ICs
R2043T 4-wire Serial Interface
R2043T-E2 4-wire Serial Interface
R2043K 4-wire Serial Interface
R2043K-E2 4-wire Serial Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R2033T 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3 wire interface Real-Time Clock ICs
R2033T-E2 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3 wire interface Real-Time Clock ICs
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