參數(shù)資料
型號(hào)： QR0001
文件頁(yè)數(shù)： 4/40頁(yè)
文件大小： 440K
代理商： QR0001
1.0 Signal Description
(Continued)
Pin Name
I/O
No.
Description
RxSTALL
I
1
RECEIVE STALL:
On the Client interface, when RxSTALL is asserted:
When PIPE is asserted, pipelined timing: RxS shall remain for the next clock cycle.
When PIPE is negated, non-pipelined timing: RxT will indicate a null for the next clock cycle and RxS
shall remain.
RxOE
I
1
RECEIVE OUTPUT ENABLE:
On the Client interface, when asserted, this signal enables outputs
RxS
[
31-0
]
. When negated, the RxS are TRI-STATE.
RxET
[
1:0
]
O
2
RECEIVE EARLY TYPE:
On the Client interface, this field identifies in advance whether the information
entering the Rx Port block is a head, data, frame or null.
RxNBL
[
3:0
]
O
4
RECEIVE NIBBLE:
On the Client interface, it contains one of the 16 selectable fields of two readable
internal areas (Diagnostics bits, RxS driver).
RxSEL
[
3:0
]
I
4
RECEIVE SELECT:
On the Client interface, selects one of the 16 fields appearing on the RxNBL. Codes
from 0 to 7 select 4 bit fields at the current output driver of RxS, codes of 8 or above select internal
diagnostics status bits.
V
CC
N/A
13
POWER PINS
GND
N/A
29
GROUND PINS
Note 1:
SignalName: The indicates that the signal is active low.
The following sections assume a 50 MHz ring clock. Note that the QR0001 has a maximum ring clock frequency of 33 MHz.
2.0 Basic Structure
The QuickRing Controller has two interfaces: the Ring Inter-
face and the Client Interface. Each interface has two ports.
All ports on the QR0001 are unidirectional so that incoming
and outgoing data can be queued simultaneously.
The two
Ring interface
ports are:
1. upstream port for arriving traffic,
2. downstream port for departing traffic.
The Ring Interface forms the link to other nodes on the
point-to-point QuickRing architecture. QuickRing connects
multiple nodes by attaching the upstream port of each node
to the downstream port of another node. The ring ports,
upstream and downstream, are 6 bits wide plus a clock. The
ring interface is implemented using LVDS drivers and re-
ceivers. The Ring Interface signals are not accessible from
the board except through the controller. The on board logic
connects to the QR0001 controller via the Client interface.
The two
Client Interface
ports are:
1. the transmit port for locally generated symbol streams,
and
2. the receive port for locally-absorbed symbol streams.
The transmit and receive ports have a 32-bit data path
which use TTL compatible I/Os. The Transmit (Tx) and Re-
ceive (Rx) ports each have a separate clock plus control
signals for information flow. Also, some QR0001 internal
status bits can be read through the receive interface. All on
board circuitry interfaces to the Client transmit and receive
ports, never to the Ring ports.
TL/F/11928–2
FIGURE 2.1. The QuickRing Controller has four ports
QuickRing transmits data streams between nodes on the
ring. The goal of QuickRing is to pipeline data streams and
not just to facilitate memory access. Imagine connecting
two cards together via a FIFO chip. One card can load data
into its side of the FIFO, and the other card can extract data
from the other side of the FIFO. QuickRing is logically equiv-
alent to placing a large FIFO between pairs of QuickRing
nodes. Cards connected through QuickRing form a ring. Re-
fer to Figure 2.2.
4
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