
7.0 Bridges
In a single QuickRing ring, the maximum number of nodes is
sixteen. Within a ring, the PIPE signal will most probably be
asserted for ease of interfacing to the QR0001. In a multiple
QuickRing topology, the individual rings may be connected
together through bridges. The system may implement a very
basic bridge or an intelligent bridge.
For a basic bridge implementation, two QR0001 controllers
can be directiy connected through their client ports, provid-
ing a bridge between two rings. The PIPE signal should be
negated in bridge operation so that the Rx and Tx port tim-
ing will be identical. Also, the TxOK signal is connected to
the RxSTALL signal. QR0001 timing characteristics will sup-
port bridging. However, an external flip-flop may be used to
achieve additional setup and hold time margins. For more
sophisticated bridges, external logic can implement a added
layer of protocol.
The HOP fields are used, with respect to bridges, when im-
plementing multi-ring topologies. The HOP fields may be
used as desired in a single ring topology. (i.e., To distinguish
various data streams.) Refer to Client Interface Field Defini-
tions sections for more information.
8.0 Little/Big Endian Issues
This QR0001 datasheet uses strict little-endian labeling
conventions to indicate bit positions. The device itself is nei-
ther big-endian nor little-endian. No assumption is made in
QR0001 about the relative significance of bytes within any
payload symbol.
For reference:
Big Endian: MSB(yte) of the information (data/address) is
stored at the least significant address location.
Little Endian: LSB(yte) of the information (data/address) is
stored at the least significant address location.
Table 8.0 contains Big/Little Endian formats.
TABLE 8.0. Big/Little Endian
Big Endian
MSB(it)
LSB(it)
Bit 0
Bit 31
[
24:31
]
[
0:7
]
[
8:15
]
[
16:23
]
MSB(yte)
LSB(yte)
Byte 0
Byte 1
Byte 2
Byte 3
Address:
(n)
Address:
(n
a
1)
Address:
(n
a
2)
Address:
(n
a
3)
Little Endian
MSB(it)
LSB(it)
Bit 31
[
31:24
]
Bit 0
[
23:16
]
[
15:8
]
[
7:0
]
MSB(yte)
LSB(yte)
Byte 3
Byte 2
Byte 1
Byte 0
Address:
(n
a
3)
Address:
(n
a
2)
Address:
(n
a
1)
Address:
(n)
9.0 Reset and Initialization
9.1 Reset
The controller must be reset after power up. RESET can be
released from each node in any order but only after all
nodes are simultaneously in the reset state (for the time
period of the reset pulse width: tRSPW timing parameter
Y
82). External logic should assert RESET to all nodes on
the ring during system power up or when ABORT is assert-
ed. The release of RESET to node 0 will begin the initializa-
tion process. The ring initialization proceeds to completition
only after RESET has been released to all nodes.
The first 2
non-null symbols
that appear at the receive port
are the node ID number and the largest ID on the ring. The
type associated with this information will indicate a non-null
type also. These values will be present for one clock cycle.
The information can be later retrieved by reading the Diag-
nostics Register through the RxNBL and RxSEL at any time
later.
TABLE 9.1. RxS
[
31:0
]
31
28
27
0
Node ID
1 1 1 1 àààààààààààààààà1
Max ID
1 1 1 1 àààààààààààààààà1
9.2 Node 0 Selection and Initialization
Only one QuickRing controller in a ring can be designated
as Node 0 (NODE0 asserted). For all other controllers on
the ring, NODE0 must be negated. Once the QuickRing has
completed the initialization process, the ring is ready for nor-
mal operation. During normal operation, there are no differ-
ences between node 0 and all other nodes.
9.3 Node ID Assignment
As RESET is released to each QuickRing controller, each
node receives the node ID of its upstream neighbor on
RxS
[
31:28
]
, assumes that its own address is node ID
a
1,
and passes its new node ID to its downstream neighbor.
After initialization, the first two non-null symbols that appear
at the receive port indicate to the client interface the node
ID number of the controller, and the largest ID number on
the ring. This information can be used to configure the client
interface.
The node ID (Node ID) and largest node ID in the system
(MaxID) can be read later from the internal diagnostics reg-
ister in the controller.
9.4 Sequence for Node 0
1. On release of RESET by all nodes, the controller with
the NODE0 signal asserted assigns itself to be node 0.
2. Node 0 then begins to transmit a stream of identical
symbols at the down stream port whose high order four
bits are
[
0,0,0,0
]
, whose frame bit is 1 and whose type
field is
[
0,1
]
.
3. The first downstream node to receive this symbol incre-
ments the value to
[
0,0,0,1
]
, becomes node 1,
4. then the node forwards the symbol containing a value
of 1. The type field and frame bit are not changed.
5. Each node in turn increments the value and takes on its
own unique node ID.
6. When the node 0 receives the symbol at its up stream
port, the value of the symbol is the largest ID number in
the ring.
7. Node 0 stores this value and forwards it around the
ring, but with the type field changed to
[
1,0
]
. This noti-
fies all other nodes the total number of nodes in the
ring.
8. All nodes forward this symbol stream unmodified.
25