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參數(shù)資料
| 型號： | QL82SD-PS484 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| 中文描述： | 10高速總線LVDS串行鏈路的帶寬高達(dá)5Gbps的 |
| 文件頁數(shù)： | 38/60頁 |
| 文件大?。?/td> | 3838K |
| 代理商： | QL82SD-PS484 |
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www.quicklogic.com
2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
38
ECU Block Description
ECU Block General Description
Traditional Programmable Logic architectures do not implement arithmetic functions
efficiently or effectively. These functions require high logic cell usage while garnering only
moderate performance results. By embedding a dynamically reconfigurable computational
unit, the QuickSD device can address various arithmetic functions efficiently and effectively
providing for a robust DSP platform
—
this approach offers greater performance than
traditional programmable logic implementations. The ECU block is ideal for complex DSP,
filtering, and algorithmic functions. The QuickSD device architecture will allow functionality
above and beyond that achievable using DSP processors or programmable logic devices. The
embedded block is implemented at the transistor level with the following block diagram.
Figure 48: SERDES ECU Block Diagram
ECU Mode Select
The ECU block can be configured for eight arithmetic functions via an instruction as shown
in
Table 31
. The modes for the ECU block are Dynamically Re-programmable through the
Instruction Set Sequencer.
Table 31: Instruction Set Sequencer
Instruction Set
Operation
0
0
0
Multiply
0
0
1
Multiply - Add
0
1
0
Accumulate
0
1
1
Add
1
0
0
Multiply (registered)
a
a. A[15:0] set to zero.
1
0
1
Multiply - Add (registered)
1
1
0
Multiply Accumulate
1
1
1
Add (registered)
Abus
Xbus
Ybus
16
8
8
Ibus
Sign
3
1
Rbus
17
8
8
16
16
Multiply
Add
Register
Sequencer
Memory
Logic Cell
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