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| 型號： | QL82SD-PS484 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| 中文描述： | 10高速總線LVDS串行鏈路的帶寬高達5Gbps的 |
| 文件頁數(shù)： | 22/60頁 |
| 文件大小： | 3838K |
| 代理商： | QL82SD-PS484 |
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www.quicklogic.com
2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
22
Super Logic (Flip-Flop and Combinational Circuit) AC Characteristics at
VCC = 2.5 V, TA = 25
o
C (K = 1)
Figure 28: Super Logic Cell Flip-Flop Structure
Figure 29: Combinational Delay for Logic Cell
Table 21: Logic Cells
Symbol
Parameter
Condition
Propagation delay (ns)
Fanout = 1
t
PD
t
SU
t
H
t
CLK
t
CWHI
t
CWLO
t
SET
t
RESET
t
SW
t
RW
Combinational Delay
a
Setup Time
b
a. Stated timing for worst case Propagation Delay over process variation at VCC = 2.5 V and
TA = 25 °C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the operating range.
b. These limits are derived from a representative selection of the slowest paths through the logic cell
including typical net delays. Worst case delay values for specific paths should be determined from
timing analysis of your particular design.
Figure 29
0.257
Figure 30
0.22
Hold Time
0
Clock to Q Delay
Figure 31
0.255
Clock High Time
Figure 32
0.46
Clock Low Time
0.46
Set Delay
Figure 33
0.18
Reset Delay
0.09
Set Width
0.30
Reset Width
0.30
reset
clk
d
set
q
tPD
input
output
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