- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361294 > QL8050 (Electronic Theatre Controls, Inc.) LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | QL8050 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| 中文描述： | 低功耗FPGA配合力性能密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 7/49頁 |
| 文件大?。?/td> | 739K |
| 代理商： | QL8050 |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
Preliminary
=
The modes for the ECU block are dynamically re-programmable through the programmable logic.
NOTE:
&&&
< 5
&56%%&&
$')*"-"
Instead of requiring extra components, designers simply need to instantiate one of the pre-
configured models (described in this section). The QuickLogic built-in PLLs support a wider range
of frequencies than many other PLLs. These PLLs also have the ability to support different ranges
of frequency multiplications or divisions, driving the device at a faster or slower rate than the
incoming clock frequency. When PLLs are cascaded, the clock signal must be routed off-chip
through the PLLPAD_OUT pin prior to routing into another PLL; internal routing cannot be used
for cascading PLLs.
PLLs achieve a very short clock-to-out time—generally less than 3 ns. This low clock-to-out time
is achieved by the PLL subtracting the clock tree delay through the feedback path, effectively
making the clock tree delay zero.
7%3,%
""
!'"
#(-"
./=2##
a. t
PD
, t
SU
and t
CO
do not include routing paths in/out of the ECU block.
b. Internal feedback path in ECU restricts max clk frequency to 238 MHz.
c. B [15:0] set to zero.
0
6
(
#!
0
0
0
Multiply
6.6 ns max
0
0
1
Multiply-Add
8.8 ns max
0
1
0
Accumulate
b
3.9 ns min
1.2 ns max
0
1
1
Add
3.1 ns max
1
0
0
Multiply (registered)
c
9.6 ns min
1.2 ns max
1
0
1
Multiply- Add (registered)
9.6 ns min
1.2 ns max
1
1
0
Multiply - Accumulate
9.6 ns min
1.2 ns max
1
1
1
Add (registered)
3.9 ns min
1.2 ns max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL8150 | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250 | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8325 | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL80FC-APB456C | Telecomm/Datacomm |
| QL80FC-APB456I | Telecomm/Datacomm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL80FC-APB456C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL80FC-APB456I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL80FC-APQ208C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL80FC-APQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL8150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。