參數(shù)資料
型號(hào)： QL8050
廠商： Electronic Theatre Controls, Inc.
英文描述： LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
中文描述： 低功耗FPGA配合力性能密度和嵌入式內(nèi)存
文件頁(yè)數(shù)： 22/49頁(yè)
文件大小： 739K
代理商： QL8050
Preliminary
00
##
The AC Specifications (at V
CC
= 1.8 V, TA = 25° C, Worst Case Corner,
Speed Grade = -7 (K = 1.16)) are provided from
< 5
waveforms are provided from
5
to
< 0;
. Logic Cell diagrams and
to
0=
.
$
Logic Cell
79%
+
7
#
"
t
PD
Combinatorial Delay of the longest path: time taken by the combinatorial circuit to
output
-
0.257 ns
t
SU
Setup time: time the synchronous input of the flip-flop must be stable before the
active clock edge
0.22 ns
-
t
HL
Hold time: time the synchronous input of the flip-flop must be stable after the active
clock edge
0 ns
-
t
CO
Clock-to-out delay: the amount of time taken by the flip-flop to output after the
active clock edge.
-
0.255 ns
t
CWHI
Clock High Time: required minimum time the clock stays high
0.46 ns
-
t
CWLO
Clock Low Time: required minimum time that the clock stays low
0.46 ns
-
t
SET
Set Delay: time between when the flip-flop is ”set” (high)
and when the output is consequently “set” (high)
-
0.18 ns
t
RESET
Reset Delay: time between when the flip-flop is ”reset” (low) and when the output
is consequently “reset” (low)
-
0.09 ns
t
SW
Set Width: time that the SET signal must remain high/low
0.3 ns
-
t
RW
Reset Width: time that the RESET signal must remain high/low
0.3 ns
-
相關(guān)PDF資料
PDF描述
QL8150 LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
QL8250 LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
QL8325 LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
QL80FC-APB456C Telecomm/Datacomm
QL80FC-APB456I Telecomm/Datacomm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
QL80FC-APB456C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm
QL80FC-APB456I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm
QL80FC-APQ208C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm
QL80FC-APQ208I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm
QL8150 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*