參數(shù)資料
型號: QL8050
廠商: Electronic Theatre Controls, Inc.
英文描述: LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
中文描述: 低功耗FPGA配合力性能密度和嵌入式內(nèi)存
文件頁數(shù): 38/49頁
文件大?。?/td> 739K
代理商: QL8050
Preliminary
63
Vpump
Charge Pump Disable
This pin disables the internal charge pump for lower static power
operation. To disable the charge pump, connect Vpump to 3.3 V.
If the Disable Charge Pump feature is not used, connect Vpump to
Ground. For backwards compatibility with Eclipse and EclipsePlus
devices, connect Vpump to Ground.
Vded
Voltage tolerance for clocks,
J TAG, and IOCTRL/Voltage
Drive for PLLOUT and J TAG
pins
This pin specifies the input voltage tolerance for CLK, J TAG, and
IOCTRL dedicated input pins, as well as the output voltage drive
for PLLOUT and J TAG pins. If the PLLs are used, Vded must be
the same as V
CC
PLL. For backwards compatibility with Eclipse and
EclipsePlus devices, connect Vded to 2.5 V.
VccPLL
Power Supply pin for PLL
Connect to 2.5 V supply or 3.3 V supply. For backwards
compatibility with Eclipse and EclipsePlus devices, connect to
2.5 V.
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