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參數資料
| 型號： | PXASCC |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CMOS 16-bit communications microcontroller(CMOS 16位通信微控制器) |
| 中文描述： | 的CMOS 16位微控制器通信的CMOS（16位通信微控制器） |
| 文件頁數： | 31/42頁 |
| 文件大小： | 229K |
| 代理商： | PXASCC |
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Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
31
4. To meet hold time, EDO DRAM drives data onto the bus until OE rises, or until a new falling edge of CAS.
5.
WARNING: ClkOut is specified at 40pF max
. More than 40pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance
for all outputs (except ClkOut) = 80pF.
6. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-SCC User Manualfor details.
7. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16 bit bus,
A3–A1 are incremented for each new word of the burst. On an 8 bit bus, A3–A0 are incremented for each new byte of the burst code fetch.
8. t
is specified as the minimum high time (thus inactive) on each of the 5 individual CS_RAS[5:1] pins when such pin is programmed in the
memory controller to service DRAM. The number of CClks (system clocks) in t
RP
is programmable, and is represented by n in the t
RP
equation in the AC tables. Regardless of what value is programmed into the control register, n will never be less than 2 clocks. Thus at
30MHz system clock, the minimum value for RAS precharge is t
RP
= ((2 * t
C
) –16) = ((2 * 33.33) – 16) = 50.6ns. As the system clock
frequency F
C
, is slowed down, t
C
(system clock period) of course becomes greater, and thus t
RP
becomes greater.
9. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a
maximum value is specified in the table for this parameter, it is tested.
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