參數(shù)資料
型號： PXASCC
廠商： NXP Semiconductors N.V.
英文描述： CMOS 16-bit communications microcontroller(CMOS 16位通信微控制器)
中文描述： 的CMOS 16位微控制器通信的CMOS（16位通信微控制器）
文件頁數(shù)： 14/42頁
文件大?。?/td> 229K
代理商： PXASCC
Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
14
MMR Name
Reset
Value
Description
Address
Offset
Size
Read/Write or
Read Only
Buffer Bound Register Ch.1 Rx
Address Pointer Reg Ch.1 Rx
Byte Count Register Ch.1 Rx
R/W
R/W
R/W
16
16
16
116h
118h
11Ah
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
11Ch = Byte 0 = older,
11Dh = Byte 1 = younger
11Eh = Byte 2 = older,
11Fh = Byte 3 = younger
Control Register
Control & Status Register
Points to 64K data segment
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
12Ch = Byte 0 = older,
12Dh = Byte 1 = younger
12Eh = Byte 2 = older,
12Fh = Byte 3 = younger
Control Register
Control & Status Register
Points to 64K data segment
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
13Ch = Byte 0 = older,
13Dh = Byte 1 = younger
13Eh = Byte 2 = older,
13Fh = Byte 3 = younger
0000h
0000h
0000h
Data FIFO Register Ch.1 Lo Rx
R/W
16
11Ch
00h
00h
00h
00h
00h
00h
00h
00h
Data FIFO Register Ch.1 Hi Rx
R/W
16
11Eh
DMA Control Register Ch.2 Rx
FIFO Control & Status Register Ch.2 Rx
Segment Register Ch. 2 Rx
Buffer Base Register Ch. 2 Rx
R/W
R/W
R/W
R/W
8
8
8
8
120h
121h
122h
124h
Buffer Bound Register Ch.2 Rx
Address Pointer Reg Ch.2 Rx
Byte Count Register Ch.2 Rx
R/W
R/W
R/W
16
16
16
126h
128h
12Ah
0000h
0000h
0000h
Data FIFO Register Ch.2 Lo Rx
R/W
16
12Ch
00h
00h
00h
00h
00h
00h
00h
00h
Data FIFO Register Ch.2 Hi Rx
R/W
16
12Eh
DMA Control Register Ch.3 Rx
FIFO Control & Status Register Ch.3 Rx
Segment Register Ch. 3 Rx
Buffer Base Register Ch. 3 Rx
R/W
R/W
R/W
R/W
8
8
8
8
130h
131h
132h
134h
Buffer Bound Register Ch.3 Rx
Address Pointer Reg Ch.3 Rx
Byte Count Register Ch.3 Rx
R/W
R/W
R/W
16
16
16
136h
138h
13Ah
0000h
0000h
0000h
Data FIFO Register Ch.3 Lo Rx
R/W
16
13Ch
00h
00h
00h
00h
Data FIFO Register Ch.3 Hi Rx
R/W
16
13Eh
Tx DMA Registers
8
8
8
8
DMA Control Register Ch.0 Tx
FIFO Control & Status Register Ch.0 Tx
Segment Register Ch. 0 Tx
Buffer Base Register Ch. 0 Tx
R/W
R/W
R/W
R/W
140h
141h
142h
144h
Control Register
Control & Status Register
Points to 64K data segment
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
14C = Byte0 = older
14D = Byte 1 = younger
14E = Byte2 = older
14F = Byte3 = younger
Control Register
Control & Status Register
Points to 64K data segment
00h
00h
00h
00h
Buffer Bound Register Ch.0 Tx
Address Pointer Reg Ch.0 Tx
Byte Count Register Ch.0 Tx
R/W
R/W
R/W
16
16
16
146h
148h
14Ah
0000h
0000h
0000h
Data FIFO Register Ch.0 Tx
R/W
16
14Ch
0000h
Data FIFO Register Ch.0 Tx
R/W
16
14Eh
0000h
DMA Control Register Ch.1 Tx
FIFO Control & Status Register Ch.1 Tx
Segment Register Ch.1 Tx
R/W
R/W
R/W
8
8
8
150h
151h
152h
00h
00h
00h
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