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參數(shù)資料
| 型號： | PUCC3801 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Current-mode PWM controller |
| 中文描述： | 電流模式PWM控制器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 308K |
| 代理商： | PUCC3801 |
Philips Semiconductors
PUCC3801
Current-mode PWM controller
Product data
Rev. 01 — 10 September 2001
5 of 16
9397 750 08419
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
With reference to
Figure 4
, assume that V
DD
is rising slowly from zero to 12 V. The
Power Manager produces a Power-On Reset (POR) signal that is routed to every
flip-flop and counter in the device. This signal is made active as early as possible in
the power-up sequence to ensure that the internal logic is reset and the device
powers up in a known state.
The POR remains active until the bandgap reference voltage (V
bandgap
) stabilizes and
the comparators in the power manager block have all settled into stable states. The
POR signal is then released and, once the supply voltage, V
DD
reaches 10 V, the
controller section is enabled and the device starts to produce output pulses.
Over-voltage and under-voltage functions:
Figure 5
shows the over-voltage trip
sequence.
A coarse internal supply V
REG
is generated by the VREG section. In standby mode,
this supply drops to a low level, typically 3 V, and the current into the V
DD
pin is limited
to a low value, less than 70
μ
A.
Fig 4.
Power-up sequence.
Fig 5.
Over-voltage and under-voltage functions.
03af32
12.0
10.0
VDD
(V)
POR
VREG
VDD(comp)
(V)
VDD(comp)
VREG
POR
Vbandgap
(V)
4.0
2.0
6.0
5.0
2.0
1.0
3.0
2.5
1.0
0
50
100
150
time
200
250
300
0.5
(μs)
Vbandgap
VDD
VREG
VREG = 3 V (off)
VREG = 6 V (on)
6 V
3 V
IDD
70
μ
A
1.2mA
70
μ
A
1.2mA
VOUT
VDD
14 V
10 V
10 V
regulated VDD = 12V
5 V
03af33
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