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參數(shù)資料
| 型號： | PUCC3801 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Current-mode PWM controller |
| 中文描述： | 電流模式PWM控制器 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 308K |
| 代理商： | PUCC3801 |
Philips Semiconductors
PUCC3801
Current-mode PWM controller
Product data
Rev. 01 — 10 September 2001
4 of 16
9397 750 08419
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
7.1.3
Current sense input pin (CSNS)
The signal on the current sense input pin is connected to the input of the pulse width
modulator comparator. A low pass filter suppresses transients and noise on the
leading edge of the current sense signal. Inside the PWM, a slope compensation
ramp, derived from the main oscillator (OSC) is added to the current sense signal.
The internal slope compensation feature allows stable operation of the converter at
duty cycles greater than 50%.
The signal on the current sense input pin is also connected to the input of an
over-current comparator. If the amplitude of the current sense signal exceeds 1.25 V,
the comparator detects an overload condition and immediately terminates the output
pulse. The propagation delay from CSNS to output, in an over-current condition, is
typically 170 ns.
7.1.4
Common circuit ground pin (GND)
This is the common power and signal ground connection. The power and signal
grounds are separated internally for improved noise immunity.
7.1.5
Gate drive output pin (OUT)
When no output pulses are being produced, this pin is held LOW. An external
pull-down resistor on the MOSFET gate is not required.
7.1.6
Positive supply voltage pin (V
DD
)
An internal shunt regulator allows the device to be powered via a resistor from a
widely varying supply. The device power management section keeps the device in
start-up current mode whilst V
DD
is ramping up. When the supply voltage reaches the
start-up threshold, the device turns on and draws the specified supply current. If V
DD
drops below the under-voltage lockout threshold, the device returns to start-up
current mode.
7.1.7
Voltage regulator pin (REG)
This is a decoupling pin for the internal low voltage supply (V
REG
). This pin must not
be loaded during start-up or whilst the device is in start-up current mode.
7.2 Device sections
The device can be considered as two sections (see
Figure 1
):
Power-up section
consisting of the POWER MANAGER, VREG, VCC, OV LATCH
and VDD
(comp)
circuitry. This part is always active.
Controller section
consisting of the ERRAMP, PWM, DRIVER, OSC, RANDOM
and OVERCURRENT COMPARATOR. This part is supplied by an internally
generated 5 V supply (V
CC
), controlled by the power-up section. The controller
section is kept switched off during power-up to minimize the start-up current.
7.2.1
Power-up section
Power-up sequence:
The power-up sequence disables the controller section and
keeps the start-up current below 70
μ
A until V
DD
rises above 10 V.
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