參數(shù)資料
型號(hào)： PT8R1202
廠商： Electronic Theatre Controls, Inc.
英文描述： Bluetooth Digital Audio Streaming IC
中文描述： 藍(lán)牙技術(shù)的數(shù)字音頻集成電路
文件頁(yè)數(shù)： 7/26頁(yè)
文件大?。?/td> 656K
代理商： PT8R1202
PT0137(08/04)
Ver:4
7
Data Sheet
PT8R1202
PT
Peric om Technology Inc .
Bluetooth Digital Audio Streaming IC
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Pin Name
PIN
I/O
TYPE
DIGITAL AUDIO INTERFACE : 9
PCMOUT / GPD[0]
J3
DO / DP
serial data
PCMIN / GPD[1]
J1
DI / DP
serial data
PCMSYNC / GPD[2]
J2
DP
clock
PCMCLK / GPD[3]
K1
DP
clock
AUDSCLK / GPD[4]
K2
DP
clock
AUDLRCLK / GPD[5]
L1
DP
clock/
AUDOUT / GPD[6]
L2
DO / DP
serial data
AUDMCLK / GPD[7]
M1
DP
clock
AUDIN / SPDIFIN/GPD[8]
K3
DI / DP
serial data
ANALOG AUDIO INTERFACE : 6
(see note9
)
MIC_IN
B2
AAI
analog
MICGS
A1
AAO
analog
VMID
C3
AAO
analog
VREF
C2
AAO
analog
EARA
C4
AAO
analog
EARB
B1
AAO
analog
SMARTMEDIA INTERFACE : 14
SM_CSB / GPE[0]
L3
DO / DP
active low
SM_CLE / GPE[1]
M2
DO / DP
active low
SM_ALE / GPE[2]
M3
DO / DP
active low
SM_WE / GPE[3]
K4
DO / DP
active low
SM_OE / GPE[4]
M4
DO / DP
active low
SM_RB / GPE[5]
L4
DI / DP
control pin
SM_DATA[7:0] /GPF[7:0]
(see note10)
DB
bus
GPIO INTERFACE : 7
GPG[0] / IRQ0 / SSM1
D6
DI / DP
active high
GPG[1] / IRQ1
B6
DI / DP
active high
GPG[2] / WAKEUP
C6
DI / DP
active high
GPG[3] / SSM0
A5
DO / DP
clock
GPG[4] / CLK32K
D5
DB / DP
signal
SPDIFO / GPG[5]
B5
DO / DP
signal
POWER SUPPLIES : 31
SPLL_VCC(1)
L11
ACP
power
SPLL_GND(1)
M12
ACG
ground
APLL_VCC(1)
D3
ACP
power
APLL_GND(1)
D2
ACG
ground
ACODEC_VCC(1)
A2
AAP
power
ACODEC_GND(2)
A3, B3
AAG
ground
VCC(6)
(see note15)
DCP
power
VCC_GND(6)
(see note16)
DCG
ground
VPP(6)
(see note17)
DPP
power
VPP_GND(6)
(see note18)
DPG
ground
Description
PCM 8kbps data out
PCM 8kbps data input
PCM 8KHz frame synchronization signal
PCM bit data clock (128/256)
audio serial data bit clock(64*fs)
audio left/right sync clock(fs)
audio serial data output
audio oversampled clock(256/384*fs)
audio serial data input
Reserved
Reserved
Reserved
Reserved
Sleep crystal(32.768kHz) XTALIN
Sleep crystal(32.768kHz) XTALOUT
Smartmedia chip select
Smartmedia command latch enable
Smartmedia address latch enable
Smartmedia write enable
Smartmedia read enable
Smartmedia ready signal
Smartmedia data/address bus
external interrupt request0 (see note11)
external interrupt request1 / USBVPI
external wake up signal (see note12) / USBRCV
Size indicator at Smartmedia boot (see note11) / USBVMI
External RTC clock(32kHz) input (see note13)
SPDIF output / USBSUSPND (see note14)
supply for system PLL (1.8V)
ground for system PLL
supply for audio PLL (1.8V)
ground for audio PLL
supply for combo audio codec (3.0V)
ground for combo audio codec
power for digital core block (1.8V)
ground for digital core block
supply for digital peripheral blocks (3.3V)
ground for digital peripheral blocks
Note :
1.
PT8R1202 use two main clocks for core operation and peripheral operation. Both clocks can be generated from on-chip PLL or
individually pumped from external clock source. The clock for processor operation, named CLKSYS, can be variable by application
requirement or dynamic power management, but the clock for peripheral operation must be fixed as 48MHz for USB and audio interface
and 32MHz for others. The PLL in the PT8R1202 supports 12MHz, 13MHz, 16MHz, or 19.2MHz as reference clock. Following table
shows the configuration of PT8R1202 clock generation block. For using internal clock from on-chip PLL, PLLSEL must be set “0”.
When using internal clock from on-chip PLL, PT8R1202 can change the operating frequency of on-chip processor up to 128MHz turbo
mode. The default operation mode is normal execution at 96MHz operating frequency and it can be changed into turbo mode by software.
However, in the case of using external clock source, it does not support turbo mode.
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