參數(shù)資料
型號: PT8R1202
廠商: Electronic Theatre Controls, Inc.
英文描述: Bluetooth Digital Audio Streaming IC
中文描述: 藍牙技術的數(shù)字音頻集成電路
文件頁數(shù): 18/26頁
文件大?。?/td> 656K
代理商: PT8R1202
PT0137(08/04)
Ver:4
18
Data Sheet
PT8R1202
PT
Peric om Technology Inc .
Bluetooth Digital Audio Streaming IC
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External Audio ADC/DAC, SPDIF input interface
Audio ADC/DAC interface provides a high quality multi resolution(16/18/20/24-bit) digital audio connection to external audio
devices. ADI interface supports I2S audio format as well as optional left-justified or right-justified audio format. ADI interface
produces one 64-bit frame at the audio sample frequency using a bit clock and frame sync signal in master mode. In slave mode,
ADI accepts one 64-bit frame in audio DAC or one 64/48-bit frame at the audio sample frequency using external generated
control signal. ADI interface supports several audio sampling frequency up to 96-kHz such as 32, 44.1, 48, 64, 88.2, or 96-kHz,
of which 256 or 384 times main clock can be generated from on-chip audio PLL or external clock signal by interface mode
programming. ADI interface contains dual on-chip FIFO which size contains maximally 2048 samples with 16-bit or 1024
samples with above 16-bit stereo audio data through YMEM2 shared with RISC/DSP processor.
Table 9. Audio interface pin description
Pin Name
AUDMCLK
I/O
programmable
Type
clock
Description
audio oversampled clock
This clock can be programmed 256 or 384 times AUDLRCLK
audio serial data bit clock
This clock is fixed at 64 times AUDLRCLK in output, but can be programmed at 64 or 48
times AUDLRCLK or UARTRTS in input
audio frame synchronization clock
This clock can be programmed up to 96kHz
audio serial data used for sending playback data to DAC
audio serial data used for receiving recording data from ADC
SPDIF serial data input
audio input serial data bit clock
This pin can be programmed as alternative audio serial data bit clock for audio input interface
audio input frame synchronization clock
This pin can be programmed as alternative audio frame synchronization for audio input
interface
AUDSCLK
programmable
clock
AUDLRCLK
programmable
clock
AUDOUT
AUDIN
output
input
serial data
serial data
UARTRTS
programmable
clock
UARTCTS
programmable
clock
MS
MS-1 MS-2
2
1
LS
MS
MS-1 MS-2
2
1
LS
Left
Right
I
2
S interface
AUDLRCLK
AUDOUT
AUDSCLK
Audio Output : 32 AUDBCLK
Audio Input : Any(24, 32) AUDBCLK
MS
MS-1 MS-2
2
1
LS
MS
MS-1 MS-2
2
1
LS
Left
Right
Left-justified interface
AUDLRCLK
AUDOUT
AUDSCLK
Audio Output : 32 AUDBCLK
Audio Input : Any(24, 32) AUDBCLK
MS
MS-1 MS-2
2
1
LS
MS
MS-1 MS-2
2
1
LS
Left
Right
Right-justified interface
AUDLRCLK
AUDOUT
AUSCLK
MS
MS
Audio Output : 32 AUDBCLK
Audio Input : 24, 32 AUDBCLK
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