PT0137(08/04)

Ver:4

19

Data Sheet

PT8R1202

PT

Peric om Technology Inc .

Bluetooth Digital Audio Streaming IC

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SPDIF interface

The PT8R1202 supports IEC-958 or SPDIF serial digital input or output data directly. Through SPDIF interface, uncompressed

audio PCM or compressed PCM can be transferred into or from the PT8R1202 in order to do wireless audio streaming solution.

The function of SPDIF and I2S input shall be executed in the time share way. The function of SPDIF and I2S output can be

executed in the same time. Following figure shows the supported data format in the PT8R1202.

USB interface

USB controller in PT8R1202 is compliant USB 1.1 version. The USB functionality is executed by an USB hardware block and

firmware running on V6 RISC processor. This configuration allows acceleration of the intensive function processing while

allowing flexibility in the implementation of higher level protocols over USB. USB controller in PT8R1202 supports both

12Mbps high speed mode and 1.5Mbps low speed mode and host and device mode programmed by firmware.

The USB hardware block consists of a serial interface engine(SIE), a serial bus controller(SBC) and a V6PB bus interface. The

SIE performs the clock/data separation, NRZI encoding and decoding, bit stuffing and unstuffing, CRC generation and checking

and the serial-parallel data conversion. The SBC consists of protocol engine and a USB device with nine endpoints including

endpoint0 for control, each with single or double buffered scheme. Control endpoint consists of single 16-byte FIFO for transmit

and receive, and eight endpoints consist of dual 64-byte FIFOs in each side, which is shared through XMEM2 with on-chip

RISC processor. Four of eight endpoints are for transmit and others for receiving. Additionally, there are four endpoints

dedicated to isochronous operation with 1023-byte FIFO located in XMEM2. The SBC manages the device address, monitors

the status of the transactions, manage the FIFOs and communicates to the processor through a set of status and control registers.

The V6PB bus interface connects the serial bus controller to the processor.

z

Endpoint 0 (EP0) : Control Endpoint equipped with 16bytes single-buffered FIFO

z

Endpoint 1 (EP1) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

z

Endpoint 2 (EP2) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

z

Endpoint 3 (EP3) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

z

Endpoint 4 (EP4) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

z

Endpoint 5 (EP5) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

z

Endpoint 6 (EP6) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

Endpoint 7 (EP7) : OUT Endpoint (isochronous) with 1023bytes single-buffered FIFO

z

Endpoint 8 (EP8) : IN Endpoint (isochronous) with 1023bytes single-buffered FIFO

z

Endpoint 9 (EP9) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

z

Endpoint 10 (EP10) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

z

Endpoint 11 (EP11) : OUT Endpoint (isochronous) with 1023bytes single-buffered FIFO

z

Endpoint 12 (EP12) : IN Endpoint (isochronous) with 1023bytes single-buffered FIFO

Preamble Aux Data LSB Audio Data MSB V U C P

Sub-frame

31

27

8

7

4

3

0

Validity

User Data

Channel Status Data

Parity Bit

X

Channel A

Y

Channel B

Z

Channel A

Y

Channel B

X

Channel A

Y

Channel B

Sub-frame

Sub-frame

Frame 191

Frame 0

Frame 1

Start of Channel Status Block