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參數(shù)資料
| 型號： | PSICS9169-01 |
| 英文描述： | Frequency Generator and Integrated Buffers for Intel Pentium and Pentium ProTM mPs |
| 中文描述： | 頻率發(fā)生器和集成緩沖器的英特爾奔騰和奔騰ProTM國會議員 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 177K |
| 代理商： | PSICS9169-01 |
7
ICS9169-01
AC Characteristics
TEST CONDITIONS
20pF load, 0.8 to 2.0V
PCLK & BCLK
20pF load, 2.0 to 0.8V
PCLK & BCLK
20pF load, 20% to 80%
PCLK & BCLK
20pF load, 80% to 20%
PCLK & BCLK
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Rise Time
1
T
r1
-
0.55
0.95
ns
Fall Time
1
T
f1
-
0.52
0.90
ns
Rise Time
1
T
r2
-
1.2
2.1
ns
Fall Time
1
T
f2
-
1.1
2.0
ns
Duty Cycle
1
D
t1
20pF load @ V
OUT
= 50% of V
DD
45
50
55
%
Duty Cycle
1
D
t2
20pF load @ V
OUT
= 1.4 V
50
55
60
%
Jitter, One Sigma
1
T
j1s1
PCLK & BCLK Clocks; Load=20pF;
R=33
F
OUT
> 25 MHz
-
50
150
ps
Jitter, Absolute
1
T
jab1
PCLK & BCLK Clocks; Load=20pF;
R=33
F
OUT
> 25 MHz
-250
-
250
ps
Jitter, One Sigma
1
T
jis2
Fixed CLK; Load=20pF
R=33
Fixed CLK; Load=20pF
R=33
-
1
3
%
Jitter, Absolute
1
T
jab2
-5
2
5
%
Input Frequency
1
F
i
12.0
14.318
16.0
MHz
Logic Input Capacitance
1
C
IN
Logic input pins
-
5
-
pF
Crystal Oscillator
Capacitance
1
C
INX
X1, X2 pins
-
18
-
pF
Power-on Time
1
t
on
From V=1.6V to 1st crossing of 66.5
MHz V
DD
supply ramp < 40 ms
-
2.5
4.5
ms
Frequency Settling Time
1
t
s
From 1st crossing of acquisition to
< 1% settling
-
2.0
4.0
ms
Clock Skew Window
1
T
sk1
PCLK to PCLK;
Load=20pF; @1.4V
BCLK to BCLK;
Load=20pF; @1.4V
PCLK to BCLK;
Load=20pF; @1.4V
-
150
250
ps
Clock Skew Window
1
T
sk2
-
300
500
ps
Clock Skew Window
1
T
sk3
1
2.6
5
ns
Electrical Characteristics at 5.0 V
V
DD
= 4.5 - 5.5 V, T
A
= 0 - 70
o
C unless otherwise stated
Note 1:
Parameter is guaranteed by design and characterization. Not 100% tested in production.
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