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參數(shù)資料
| 型號： | PSD813FH |
| 英文描述： | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器) |
| 中文描述： | 場可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器） |
| 文件頁數(shù)： | 45/83頁 |
| 文件大?。?/td> | 369K |
| 代理商： | PSD813FH |
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Prelimnary
PSD813FN/FH
45
The PSD813FN/FH offers a number of configurable power savings options. The designer
may choose a wide array of options that range from excellent power savings with no
performance loss to maximum power savings at the expense of a slight performance loss.
These power saving functions are designed to occur automatically in the background and
most can be set up by the MCU at Run-Time. Note that these features only apply to the
PSD6XX portion of this Multi-Chip Module. The monolithic PSD8XXF members will apply
these power reduction features to the NVM sections as well.
The Automatic Power Down (APD) Mode
APD logic puts the PSD813FN/FH into power savings mode by monitoring the activity of
the address strobe (ALE/AS). The APD unit is a down-counter that is reset by the active
state of ALE/AS. See Figure 20. This APD counter is clocked by an external free running
clock signal that is routed in on the CLKIN pin (Port D-PD1). The APD counter will reach
terminal count after 15 transitions of CLKIN. If ALE/AS is not active for 15 cycles of CLKIN,
the APD counter will reach terminal count and force Power Down Mode if enabled. The
PSD will come out of Power Down mode immediately after the first active pulse of ALE/AS
with no performance penalty.
During Power Down mode, the PSD Boot EPROM, SRAM, and MCU bus interface is
disabled. The GPLD and ECSPLD sections operate as normal during Power Down mode.
Table 26 shows the effects of Power Down mode on PSD I/O.
Power
Management
Unit
Port Function
Pin Level
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
No Change
No Change
Undefined
Hi-Z Tri-State
Hi-Z Tri-State
Table 26. Power Down Effect on Ports
APD functions are enabled by the MCU at Run-Time using the Power Management Mode
Registers PMMR0 and PMMR1 as shown in Table 28. Figure 21 shows a typical flow for
mode setup. Power Down mode may also be achieved by deasserting the CSI input as
described later.
Sleep Mode
Sleep Mode is an extension of Power Down mode which provides maximum power
savings at the expense of a small performance loss. If Sleep mode is enabled, Sleep mode
will occur when Power Down mode occurs and exit when Power Down mode exits.
In Sleep mode, the GPLD and ECSPLD still monitor inputs and respond to them, however,
the GPLD and ECSPLD propagation delays are extended to t
PD4
. When Sleep mode is
exited, the GPLD and ECSPLD will continue to have the extended delay of t
PD4
for a
“wake-up” period of t
PD5
. Also, the first access of Boot EPROM or SRAM that occurs while
coming out of sleep mode will incur an extended access time of t
LVDV1
. After that, PSD
EPROM and SRAM access times will be normal.
Sleep mode is enabled by the MCU at Run-Time using the Power Management Mode
Register PMMR1 as shown in Table 28. Figure 21 also shows a typical flow for mode setup.
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相關(guān)代理商/技術(shù)參數(shù) |
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| PSD813FH-15J | 制造商:WSI 功能描述: |
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| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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