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| 型號： | PSD703S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個可編程輸入/輸出，通用PLD的有66個輸入） |
| 文件頁數(shù)： | 65/104頁 |
| 文件大?。?/td> | 515K |
| 代理商： | PSD703S5 |
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PSD7XX Family
13-65
Supervisory
Function
The Supervisory Function in the PSD7XX significantly improves microcontroller system
reliability with programmable features such as power supply monitoring, reset control and
WatchDog Timer.
These features are:
J
5% and 10% power supply monitoring
J
Reset generation based on various conditions:
– Power-On reset; voltage comparator with programmable internal or external trip point
– Push Button or System reset input
– WatchDog Timer output
J
User programmable WatchDog Timer (controlled by PPLD product terms).
J
Battery-backup of internal SRAM.
J
Write protect of internal SRAM and external memory.
J
Reset input debouncer filter.
J
Programmable reset pulse width generator
Figure 31 is the block diagram of the Supervisory Function. The input and output
supervisory pins are listed in Table 35. Pins that are not used can be configured for other
PSD7XX I/O functions. Table 36 shows the inputs and outputs of the PPLD that are involved
in controlling the Supervisory Function.
Input Pin
Output Pin
Pin Name
Description
Pin Name
Description
VSTBY (PC2)
SRAM Battery Backup
input
VSTBYON (PC4)
Pin is driven high
when PSD7XX is
switched over to
Standby Voltage
VTRIP (PC6)
External Trip voltage
input for the voltage
comparator
CEOUT (PC3)
Chip select output
that can be used for
external non-volatile
writable memory. This
chip select becomes
inactive automatically
when the PSD7XX
is switched to standby
voltage. Use to
conserve power in
external battery backup
SRAM or prevent
unwanted writes to
external EEPROM,
SRAM, or FLASH.
RESET
System or push button
reset input
RST_OUT (PC5)
Active high reset
output
CLKIN (PD1)
External clock input
RST_OUT (PC1)
Active low reset output
Table 35. Supervisory I/O Pins
相關(guān)PDF資料 |
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| PSD701S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
| PSD702S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
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| PSD712S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
| PSD713S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
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