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| 型號(hào)： | PSD702S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入） |
| 文件頁(yè)數(shù)： | 48/104頁(yè) |
| 文件大?。?/td> | 515K |
| 代理商： | PSD702S5 |
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PSD7XX Family
13-48
I/O Ports
(cont.)
Port Registers
(cont.)
Drive Register
The Drive Register configures the pin driver as Open Drain, or in the case of ECSPLD
outputs, sets the pin to operate in high slew rate. An external pull-up resistor is not required
when the pin is in the slew rate mode.
For Ports A and B the register sets different functions for the lower and higher nibbles. The
four upper bits set the corresponding bits as CMOS (“0”) or Open Drain (“1”) driver. The
four lower bits are used for slew rate control. The slew rate is a measurement of the rise
and fall times of the output. A higher slew rate means a faster output response while a lower
slew rate is a slower, lower slope, response. The pin operates in high slew rate when the
corresponding bit in the Drive Register is set to “1”.
Table 26 shows the Drive Registers of Port A, B, C and D and which pin has the Open Drain
or Slew Rate configuration.
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port D
NA
NA
NA
NA
NA
Slew
Rate
Slew
Rate
Slew
Rate
Table 26. Drive Register Pin Assignment
NOTE:
NA = Not Applicable, bit should set to “0”.
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