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    參數(shù)資料
    型號(hào): PSD702S5
    英文描述: Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
    中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能(可編程邏輯,4K的位的SRAM,27余個(gè)可編程輸入/輸出,通用PLD的有66個(gè)輸入)
    文件頁數(shù): 13/104頁
    文件大?。?/td> 515K
    代理商: PSD702S5
    PSD7XX Family
    13-13
    PSD7XX
    Architectural
    Overview
    (cont.)
    Microcontroller Bus Interface
    The PSD7XX easily interfaces with most popular eight and sixteen-bit microcontrollers
    with either multiplexed or non-multiplexed address/data busses. The device is configured to
    respond to the microcontroller control signals which are also used as inputs to the PLDs.
    Memory
    The PSD7XX contains EPROM and SRAM. The EPROM densities available are 256 Kbit,
    512 Kbit and 1 Mbit. The memory space is divided into eight equally-sized blocks. Each
    block can be located in a different address space defined by the user. The access time of
    the EPROM includes the address latching and DPLD decoding.
    The 4 Kbit SRAM may be used as a scratch pad memory and an extension of the
    microcontroller SRAM. The SRAM data is retained in the event of a system power down,
    provided a backup battery is connected to the Vstby pin (PC2). Switching from the V
    CC
    supply to standby power occurs automatically when V
    CC
    drops below Vstby voltage.
    Page Register
    The four-bit Page Register expands the address range of the microcontroller by sixteen
    times. The paged address can be used as part of the address space to access external
    memory and peripherals or internal EPROM, SRAM and I/O.
    Power Management Unit
    The Power Management Unit (PMU) in the PSD7XX enables the user to control the
    power consumption on selected functional blocks based on system requirements. The PMU
    includes an Automatic Power Down unit (APD) that will turn off device functions due to
    microcontroller inactivity in one of two modes: the Power Down mode and Sleep mode.
    Other power saving features, such as the CMiser in the PMU, allow the EPROM/SRAM to
    operate at a slower rate to conserve power.
    相關(guān)PDF資料
    PDF描述
    PSD711S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
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