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參數(shù)資料
| 型號： | PSD702S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個可編程輸入/輸出，通用PLD的有66個輸入） |
| 文件頁數(shù)： | 47/104頁 |
| 文件大?。?/td> | 515K |
| 代理商： | PSD702S5 |
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PSD7XX Family
13-47
I/O Ports
(cont.)
Port Registers
Each port has a set of registers used for configuration (PCR, Port Configuration Registers)
and data transfers (PDR, Port Data Registers). The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Tables 28 and 28a. The register addresses are comprised of the CSIOP output
from the DPLD plus an address offset as listed in the tables.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 in its port. The three Port
Configuration Registers, shown in Table 24, are used for setting the port configuration. Each
register is set to zero at power up.
Register Name
Port
MCU Access
Control
Direction
Drive*
A,B
A,B,C,D
A,B,C,D
Write/Read
Write/Read
Write/Read
Table 24. Port Configuration Registers
*
Note: See Table 25 for Drive Register bit definition.
Control Register
A zero in the Control Register sets the Port pin to MCU I/O for Port A and B. A “1” sets the
Port pin to Address Out mode. The default mode is MCU I/O.
Direction Register
Controls the direction of data flow in the I/O Ports. A “1” configures the port to be an
output, and a “0” to an input. The I/O configuration can be read from the Direction Register.
The default mode is input.
As shown in the Port Architecture diagram, the direction of data flow in Port A,B and C pins
are also controlled by the output enable (.oe) product term from the GPLD AND array. If the
.oe product term is not active, the Direction Register has sole control of the pin direction.
An example of a configuration for a port with the three least significant bits set to output
and the remainder set to input is shown in Table 25. The Port D register has only the three
least significant bits active.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
Table 25. Port Direction Assignment Example
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