- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368231 > PSD611E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) PDF資料下載
參數(shù)資料
| 型號： | PSD611E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入） |
| 文件頁數(shù)： | 61/84頁 |
| 文件大?。?/td> | 426K |
| 代理商： | PSD611E1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當(dāng)前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
PSD6XX Family
11-61
Port Configuration
Reset
Power Down Mode
MCU I/O
Input
Unchanged
PLD Output
Active
Depends on inputs to the PLD
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Register
Reset
Power Down Mode
PMMR0 & 1
Cleared (power up reset)
Unchanged (warm reset)
Unchanged
Micro
Cells Flip-Flop
Unchanged*
Unchanged*
All other registers
Cleared to “0”
Unchanged
Table 34. Chip Status During Reset and Power Down Mode
Power
Management
Unit
(cont.)
*
The Micro
Cell Flip-Flop can be cleared or set by the reset input or the PDN (Power Down) signal, depending on
the .re and .pr equations that are defined in the PSDabel file.
Battery Backup
The PSD6XXE1 supports a battery backup operation that retains the contents of the
SRAM in the event of a power loss. The Port PC2 pin is dedicated as the input pin for an
external power source. If the supply voltage falls below a reference voltage (Vstby), an inter-
nal power-switch occurs so that PC2 provides power to the internal SRAM. The SRAM
contents are retained down to a level of 2V.
Security Protection
The PSD6XXE1 has a programmable security bit which acts as a duplication barrier.
When the bit is set, the contents of the EPROM, non-volatile configuration bits, and PLD
cannot be read by device programmers.
The security bit is set through the PSDsoft Software and is embedded in the compiled
output file. The security bit is UV erasable and a secured windowed part can be erased
and re-programmed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD601E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| PSD602E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| PSD603E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| PSD612E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| PSD613E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD611E1-15J | 制造商:WSI 功能描述: 制造商:WSI 功能描述:32K X 8 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| PSD611E1-15L | 制造商:WSI 功能描述: |
| PSD611E1-70L | 制造商:WSI 功能描述: |
| PSD6121212 | 制造商:TDK-Lambda Corporation 功能描述:DC/DC,DUAL-OUT,12/-12V,0.25/-0.25A,6W - Bulk |
| PSD6-12-1212 | 功能描述:DC/DC轉(zhuǎn)換器 6W 12V 0.25A RoHS:否 制造商:Murata 產(chǎn)品: 輸出功率: 輸入電壓范圍:3.6 V to 5.5 V 輸入電壓（標(biāo)稱）: 輸出端數(shù)量:1 輸出電壓（通道 1）:3.3 V 輸出電流（通道 1）:600 mA 輸出電壓（通道 2）: 輸出電流（通道 2）: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體尺寸: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。