參數(shù)資料
型號(hào)： PSD611E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入）
文件頁(yè)數(shù)： 55/84頁(yè)
文件大小： 426K
代理商： PSD611E1
PSD6XX Family
11-55
The PSD6XXE1 offers a number of configurable power saving options which include the
Automatic Power Down (APD) Logic and the Power Management Mode Registers (PMMR0
and PMMR1). The APD Logic allows the PSD6XXE1 to enter into either Power Down or
Sleep Mode automatically, while the PMMRs can be configured at run time by the
microcontroller to selectively reduce the power consumption of the PSD functional blocks.
The APD Logic and Power Down Mode
The Automatic Power Down (APD) logic puts the PSD6XXE1 into power savings mode by
monitoring the activity of the address strobe (ALE/AS). If the APD unit is enabled, the
four-bit APD counter starts counting whenever the address strobe is inactive. If the strobe
remains inactive for fifteen CLKIN clock periods, the power down (PDN) signal will become
active and the PSD6XXE1 enter into either Power Down or Sleep Mode. Immediately after
ALE starts pulsing the PSD6XXE1 will return to normal operation. The APD counter clock
source comes from the CLKIN pin which is pin PD1 on Port D. In order to guarantee that the
APD counter will not overflow when enabled, there should be less than 15 clocks between
two successive ALE pulses.
Usually, microcontrollers entering power down mode will freeze their ALE at logic high or
low level. By programming bit 0 of PMMR0, the APD knows when the MCU is in power
down mode. If the APD detects the ALE level is in the power down state for 15 CLKIN
periods, then the PSD6XXE1 will enter a power down mode. To enable the APD operation,
the APD bit in the PMMR0 should be set to “1”.
When the address strobe starts pulsing again, or the CSI input switches from high to low,
the PSD6XXE1 will return to normal activity.
When the PDN signal is set to “1” (active state) in Power Down (or Sleep Mode), the
PSD6XXE1 MCU bus interface is disabled and all MCU inputs (address, data and control
signals) are blocked from entering the device. If the clock input to the PLD is not needed
in Power Down mode, it should be blocked to save power by setting Bit 4 and 5 in the
PMMR0 to “1”.
Sleep Mode
The Sleep Mode is activated if the Sleep mode bit, the APD bit and the ALE Polarity bit in
the PMMRs are set, and the APD Counter has overflowed after 15 CLKIN clocks
(see Figure 27). In Sleep Mode the PSD6XXE1 consumes less power than the Power Down
Mode, with typical I
CC
reduced to 25μA.
In this mode, the PLD still monitors the inputs and responds to them. As soon as the ALE
starts pulsing or the CSI input switches from high to low, the PSD6XXE1 exits the Sleep
Mode. The PSD6XXE1 access time from Sleep Mode is specified by tLVDV1. The PLD
response time to an input transition is specified by tLVDV2.
Power
Management
Unit
Port Function
Pin Level
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
No Change
No Change
Undefined
Three-State
Three-State
Table 30. Power Down Effect on Ports
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD611E1-15J 制造商:WSI 功能描述: 制造商:WSI 功能描述:32K X 8 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52
PSD611E1-15L 制造商:WSI 功能描述:
PSD611E1-70L 制造商:WSI 功能描述:
PSD6121212 制造商:TDK-Lambda Corporation 功能描述:DC/DC,DUAL-OUT,12/-12V,0.25/-0.25A,6W - Bulk
PSD6-12-1212 功能描述:DC/DC轉(zhuǎn)換器 6W 12V 0.25A RoHS:否 制造商:Murata 產(chǎn)品: 輸出功率: 輸入電壓范圍:3.6 V to 5.5 V 輸入電壓（標(biāo)稱(chēng)）: 輸出端數(shù)量:1 輸出電壓（通道 1）:3.3 V 輸出電流（通道 1）:600 mA 輸出電壓（通道 2）: 輸出電流（通道 2）: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體尺寸:
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