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| 型號： | PSD601E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個可編程輸入/輸出，通用PLD的有63個輸入） |
| 文件頁數(shù)： | 58/84頁 |
| 文件大?。?/td> | 426K |
| 代理商： | PSD601E1 |
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PSD6XX Family
11-58
Bit 0
0 = ALE power down polarity low
1 = ALE power down polarity high
0 = Automatic Power Down (APD) is disabled
1 = Automatic Power Down (APD) is enabled
0 = EPROM/SRAM CMiser is off
1 = EPROM/SRAM CMiser is on
0 = CLKIN input to the PLD AND array is connected
Every CLKIN change will power up the PLD when Turbo bit is off
1 = CLKIN input to PLD AND array is disconnected
0 = CLKIN input to the PLD Micro
Cells is connected
1 = CLKIN input to PLD Micro
Cells is disconnected
Bit 1
Bit 2
Bit 4
Bit 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
ZPLD
Mcell clk
ZPLD
Array clk
*
CMiser
APD
Enable
ALE PD
Polarity
1 = off
1 = off
1 = on
1 = on
1 = high
Table 32. Power Management Mode Registers (PMMR0, PMMR1)**
PMMR0
*
*
Bits 3, 6 and 7 are not used, and should set to 0.
**
Both the PMMR0 and PMMR1 register bits are clear to zero following power up.
Subsequent reset pulses will not clear the registers.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
*
*
Sleep
Mode
Enable
1 = on
*
PMMR1
Bit 1
0 = Sleep Mode is Disabled
1 = Sleep Mode is Enabled
*
Unused bits should be set to 0.
APD
ALE
Enable Bit
PD Polarity
ALE Level
APD Counter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
Table 33. APD Counter Operation
Power
Management
Unit
(cont.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD601E1-15L | 制造商:WSI 功能描述: |
| PSD601E1-70J | 制造商:WSI 功能描述: 制造商:WSI 功能描述:16K X 16 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| PSD601E1-70L | 制造商:WSI 功能描述: |
| PSD602E1-70L | 制造商:WSI 功能描述: |
| PSD603E1-70L | 制造商:WSI 功能描述: |
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