參數(shù)資料
型號： PSD601E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入）
文件頁數(shù)： 28/84頁
文件大小： 426K
代理商： PSD601E1
PSD6XX Family
11-28
Microcontroller Interface Examples
Figures 12 through 19 show examples of the basic connections between the PSD6XXE1
and some popular microcontrollers. The PSD6XXE1 control input pins are labeled as the
microcontroller function for which they are configured. The MCU interface is specified using
the PSDsoft tools. The PC2 pin should be grounded if Vstby is not used.
80C31
Figure 12 shows the interface to the 80C31 which has an 8-bit multiplexed address/data
bus. The lower address byte is multiplexed with the data bus. The microcontroller RD and
WR signals may be used for accessing internal SRAM and I/O Ports while the PSEN signal
is used to read the EPROM. The ALE input (Port D PD0) latches the address. Refer to the
Memory Section for additional 80C31 operating modes.
68HC11
Figure 13 shows an interface to an 68HC11 where the PSD6XXE1 is configured in 8-bit
multiplexed mode with E and R/W settings. The ECSPLD can generate the READ and
WR signals for external on board devices. The CNTL2 pin is not used and can be used
as a PLD input.
80C196
In Figure 14, the Intel 80C196 microcontroller, which has a multiplexed sixteen-bit bus,
is shown connected to a PSD6XXE1. The BHE signal is used for high data byte selection.
Port pins can be configured in the PSDabel as PLD outputs to control the READY and
BUSWIDTH pins of the 80C196.
MC68331
Figure 15 shows a Motorola MC68331 with non-multiplexed sixteen-bit data bus and
24-bit address bus. The data bus from the MC68331 is connected to Port A (D0–7) and
Port B (D8–15). The SIZ0 and A0 inputs determine the high/low byte selection.
80C51XA
The Philips 80C51XA microcontroller family has an 8 or 16 bit multiplexed bus that
supports burst cycles. Address bits A[3:0] are not multiplexed while A[19:4] are multiplexed
with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed with data bits
D[7:0].
The 80C51XA can be configured to operate with a PSD6XXE1 in eight-bit (shown in
Figure 16) or sixteen-bit (shown in Figure 17) data mode. With a sixteen-bit data bus, the
80C51XA’s WRH pin is connected to the PC7 pin on the PSD6XXE1. Pin PA0 is grounded
and not used.
The 80C51XA improves bus throughput and performance by executing Burst cycles to
fetch codes from memory. In Burst cycles, address A19–4 are latched internally by the
PSD6XXE1, while the 80C51XA changes the A3–0 lines to sequentially fetch up to
16 bytes of code. The PSD access time is then measured from address A3–A0 valid
to data in valid. The PSD6XXE1 bus timing requirement in Burst cycle is identical to the
normal bus cycle except the address set up or hold time with respect to ALE is not required.
Bus Interface
(cont.)
相關(guān)PDF資料
PDF描述
PSD602E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
PSD603E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
PSD612E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
PSD613E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
PSD703S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD601E1-15L 制造商:WSI 功能描述:
PSD601E1-70J 制造商:WSI 功能描述: 制造商:WSI 功能描述:16K X 16 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52
PSD601E1-70L 制造商:WSI 功能描述:
PSD602E1-70L 制造商:WSI 功能描述:
PSD603E1-70L 制造商:WSI 功能描述:
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