參數(shù)資料
型號(hào)： PSD413A1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有37個(gè)輸入）
文件頁(yè)數(shù)： 4/97頁(yè)
文件大?。?/td> 309K
代理商： PSD413A1
PSD4XX Famly
4-4
General
Description
(Cont.)
The general purpose PLD (GPLD) is a general purpose ZPLD that can be used to
implement state machines and logic . The GPLD has up to 59 inputs, 118 product terms,
24 flexible macrocells and 24 I/O pins that are connected to Ports A, B and E. The GPLD
can also decode the microcontroller address bus and generate chip selects to external
peripherals or memories.
The ZPLDs are designed to consume minimum power using Zero Power design techniques.
A configuration bit (Turbo bit), that can be set by the MCU, will automatically place the
ZPLDs into standby if no inputs are changing. Any unused product terms will be turned off
during programming and will not consume any power in the system.
The PSD4XX has 40 I/O pins that are divided into 5 ports. Each I/O pin can be individually
configured to provide many functions. Ports A, B and E have the capability to be configured
as standard MCU I/O ports, GPLD I/O, or latched address outputs for multiplexed
address/data controllers. Ports C and D are standard I/O ports that can also be configured
as ZPLD inputs or as a data bus for microcontrollers with a non-multiplexed bus.
The PSD4XX can easily interface with no “glue-logic” to a variety of 8 and 16-bit
microcontrollers with a multiplexed or non-multiplexed bus. All of the control signals are
connected to the two ZPLDs enabling the user to generate timing and decoding signals for
external peripherals. For controllers that do not have a Reset output, the PSD4XX can
generate a RESET output based on its RESET input. This input includes hysteresis.
The PSD4XX contains EPROM and scratchpad SRAM. The EPROM densities are
256 Kbit, 512 Kbit and 1 Mbit and are divided into four blocks. Each block can be located in
a different address location. The access time of the EPROM includes the address latching
and DPLD decoding. The 16 Kbit Standby SRAM may be used as an extension of the
microcontroller SRAM and also to store backup information that is necessary after a system
power down. Backup power to the SRAM is supplied by the Vstdby pin. Switching between
V
CC
and Vstdby occurs automatically when V
CC
power is removed.
A four bit Page Register enables easy access to the I/O Section, EPROM and SRAM for
microcontrollers with limited address space . The Page Register outputs are connected to
all ZPLDs and can be used to page external devices as well as the internal PSD4XX
functional units.
A Power Management Unit (PMU) in the PSD4XX enables the user to control the power
consumption on selected functional blocks based on system requirements. For
microcontrollers that do not generate a Chip Select input (CSI) to the peripheral device,
the PMU includes an Automatic Power Down unit (APD) that will turn off the PSD4XX
(into standby or sleep mode) based on inactivity of the ALE. The polarity of ALE inactivity
can be defined by the user. In addition to standby mode, the PSD4XX includes a SLEEP
mode that will reduce the power consumption to 10 μA.
相關(guān)PDF資料
PDF描述
PSD401A1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
PSD401A2 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD402A1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
PSD402A2 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD403A1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD413A2-C-70L 制造商:WSI 功能描述:
PSD4-16 制造商:Tamura Corporation of America 功能描述:
PSD4-20 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA
PSD4235G2-70U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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