參數(shù)資料
型號(hào)： PSD413A1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有37個(gè)輸入）
文件頁數(shù)： 29/97頁
文件大?。?/td> 309K
代理商： PSD413A1
PSD4XX Famly
4-29
Port B Macrocell Structure
Figure 15 shows the PB Macrocell block, which consists of 8 identical macrocells. Each
macrocell output can be connected to its own I/O pin on Port B. The two inputs, CLKIN and
MACRO-RST, are used as clock and clear inputs to all the macrocells. The CLKIN comes
directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin
except it is user configurable.
The circuit of a PB Macrocell is shown in Figure 16. There are 10 product terms from the
GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the output,
and configure the macrocell to operate as:
J
Registered Output
Select output from D flip flop.
J
Combinatorial Output
Select output from OR gate.
J
GPLD Input
Use Port B pin as dedicated input.
J
GPLD Output
Use Port B pin as dedicated output.
J
GPLD I/O
Use Port B pin as bidirectional pin.
J
Macrocell Feedback
Register feedback for state machine implementations or expander feedback
from the combinatorial output, to possibly expand the number of product terms
available to another macrocell.
In case of "Buried Feedback", where the output of the macrocell is not
connected to a Port B pin, Port B can be configured to perform other user
defined I/O functions.
Each D flip flop in the macrocells has its own dedicated asynchronous clear, preset and
clock input. The signals are defined as follow:
J
PRESET
Active only if defined by a product term (PBx.PR)
J
CLEAR
Two selectable inputs: Reset input or user defined product term (PBx .RE)
J
CLK
Two selectable inputs – CLKIN input or user defined product term (PBx.CLK).
The macrocell is operated in Synchronous Mode if the clock input is
CLKIN, and is in Asynchronous Mode if the clock is a product-term clock
defined by the user.
PSD4XXA2
ZPLDBlock
(Cont.)
相關(guān)PDF資料
PDF描述
PSD401A1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
PSD401A2 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD402A1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
PSD402A2 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD403A1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD413A2-C-70L 制造商:WSI 功能描述:
PSD4-16 制造商:Tamura Corporation of America 功能描述:
PSD4-20 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA
PSD4235G2-70U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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