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參數(shù)資料
| 型號： | PSD413A1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有37個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有37個輸入） |
| 文件頁數(shù)： | 2/97頁 |
| 文件大?。?/td> | 309K |
| 代理商： | PSD413A1 |
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PSD4XX Famly
4-2
Key Features
(Cont.)
J
Low power operation is achieved by using a Power Management Unit (PMU) that
enables automatic stand-by modes in the EPROM, SRAM, and ZPLDs. It also disables
the clock to the ZPLD. Also available is an automatic power down mode using the
ALE signal. A Sleep mode is available that consumes only 10 μA standby power
consumption.
J
Package choices include 68 pin plastic (J) and ceramic (L) chip carriers.
J
The PSD4XX family is supported with PC based PSDsoft MS-Windows
compatible
development tools. Offering ABEL
as a design entry method (PSDabel), an efficient
Fitter, Address Translator, MagicPro
programmer and a full chip simulator (SILOS III
from SIMUCAD) (PSDsim) are included.
The PSD4XX series of Field Programmable Microcontroller Peripherals represent a
major advance in the evolution of Programmable Peripherals. They combine an innovative
architecture with state of the art technology to provide user programmability (logic,
functions, memory), flexibility, high integration, optimum performance, and low power . For
example, the PSD413A2 can implement a full peripheral subsystem and has the following
features:
J
Two ZPLDs with a total of 59 inputs, 126 product terms outputs, 24 macrocells
and 24 I/O pins.
J
40 individually programmable I/O pins that are divided into 5 Ports.
J
4-Bit Page Register for external memory addressing
J
1 Mbit EPROM consisting of four 256 Kbit blocks.
J
16 Kbit of standby SRAM that can automatically switch into standby mode.
J
Power management unit with automatic standby and sleep modes.
J
Security mode.
Figure 1 is a top level block diagram of the PSD4XX. Refer to Table 1 and other sections for
details on functionality, DC/AC specifications, packages and ordering information.
At the core of the PSD4XX are ZPLDs dedicated to the functions they perform:
J
Decoding ZPLD (DPLD)
J
General Purpose ZPLD (GPLD)
Both ZPLDs receive the same inputs through the ZPLD bus and are differentiated by their
output destinations. The Decoder PLD (DPLD) has as its main function to perform address
space decoding for the internal I/O Ports, four blocks of EPROM, standby SRAM and
peripheral mode of Port A. The address decoding can be based on any address input,
control signal (RD, PSEN, etc.) and page logic. Address inputs originate from either the
microcontroller interface (ADIO Port) or other I/O Ports for additional decoding. The DPLD
also supports special requirements of 8031 architecture based designs that need to store
data in the EPROM or execute programs from the SRAM.
General
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD401A1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有37個輸入) |
| PSD401A2 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有59個輸入) |
| PSD402A1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有37個輸入) |
| PSD402A2 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有59個輸入) |
| PSD403A1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有37個輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD413A2-C-70L | 制造商:WSI 功能描述: |
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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