參數(shù)資料
型號(hào)： PPC5604BCLL64
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 59/109頁(yè)
文件大?。?/td> 0K
描述： MCU 32BIT 512K 64MHZ
標(biāo)準(zhǔn)包裝： 90
系列： MPC56xx Qorivva
核心處理器： e200z0h
芯體尺寸： 32-位
速度： 64MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 79
程序存儲(chǔ)器容量： 512KB（512K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 4K x 16
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 28x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤(pán)
Package pinouts and signal descriptions
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
Freescale Semiconductor
53
Example 1. No regulator (worst case)
The
VDD(STDBY)| parameter can be seen as the VDD voltage drop through the ESR resistance of the regulator stability
capacitor when the IDD_BV current required to load VDD_LV domain during the standby exit. It is thus possible to define the
maximum equivalent resistance ESRSTDBY(MAX) of the total capacitance on the VDD supply:
ESRSTDBY(MAX) = VDD(STDBY)|/IDD_BV = (30 mV)/(300 mA) = 0.1 1
The dVDD(STDBY)/dt parameter can be seen as the VDD voltage drop at the capacitance pin (excluding ESR drop) while
providing the IDD_BV supply required to load VDD_LV domain during the standby exit. It is thus possible to define the minimum
equivalent capacitance CSTDBY(MIN) of the total capacitance on the VDD supply:
CSTDBY(MIN) = IDD_BV/dVDD(STDBY)/dt = (300 mA)/(15 mV/s) = 20 F
This configuration is a worst case, with the assumption no regulator is available.
Example 2. Simplified regulator
The regulator should be able to provide significant amount of the current during the standby exit process. For example, in case
of an ideal voltage regulator providing 200 mA current, it is possible to recalculate the equivalent ESRSTDBY(MAX) and
CSTDBY(MIN) as follows:
ESRSTDBY(MAX) = VDD(STDBY)|/(IDD_BV 200 mA) = (30 mV)/(100 mA) = 0.3
CSTDBY(MIN) = (IDD_BV 200 mA)/dVDD(STDBY)/dt = (300 mA 200 mA)/(15 mV/s) = 6.7 F
In case optimization is required, CSTDBY(MIN) and ESRSTDBY(MAX) should be calculated based on the regulator
characteristics as well as the board VDD plane characteristics.
3.17.2
Low voltage detector electrical characteristics
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage
detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied:
POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state (refer to RGM
Destructive Event Status (RGM_DES) Register flag F_POR in device reference manual)
LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer to RGM Destructive Event
Status (RGM_DES) Register flag F_LVD27 in device reference manual)
LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to RGM Functional Event Status
(RGM_FES) Register flag F_LVD45 in device reference manual)
LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD1 in device reference manual
LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD0 in device reference manual)
NOTE
When enabled, power domain No. 2 is monitored through LVDLVBKP.
1. Based on typical time for standby exit sequence of 20 s, ESR(MIN) can actually be considered at ~50 kHz.
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