
60
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Revision 1.26 – April 25, 2007
Data Sheet
Input Logic High (2.5V SSTL)
V
IH
SV
REF
+0.18
SV
DD
+0.3
V
Input Logic High (2.5V CMOS, 3.3V tolerant receiver)
1.7
V
Input Logic High (3.3V PCI)
0.5OV
DD
OV
DD
+0.5
V
1
Input Logic High (3.3V LVTTL)
+2.0
+3.6
V
Input Logic Low (2.5V SSTL)
V
IL
-0.3
SV
REF
-0.18
V
Input Logic Low (2.5V CMOS, 3.3V tolerant receiver)
0.7
V
Input Logic Low (3.3V PCI)
-0.5
0.35OV
DD
V
1
Input Logic Low (3.3V LVTTL)
0
+0.8
V
Output Logic High (2.5V SSTL)
V
OH
+1.95
SV
DD
V
Output Logic High (2.5V CMOS, 3.3V tolerant receiver)
2.0
SV
DD
V
Output Logic High (3.3V PCI)
0.9OV
DD
OV
DD
V
1
Output Logic High (3.3V LVTTL)
+2.4
OV
DD
V
Output Logic Low (2.5V SSTL)
V
OL
0
0.55
V
Output Logic Low (2.5V CMOS, 3.3V tolerant receiver)
0.4
V
Output Logic Low (3.3V PCI)
0.1OV
DD
V
1
Output Logic Low (3.3V LVTTL)
0
+0.4
V
Input Leakage Current (No pull-up or pull-down)
I
IL1
0
0
μ
A
Input Leakage Current for Pull-Down
I
IL2
0 (LPDL)
200 (MPUL)
μ
A
Input Leakage Current for Pull-Up
I
IL3
-150 (LPDL)
0 (MPUL)
μ
A
Input Max Allowable Overshoot (3.3V LVTTL)
V
IMAO
+3.9
V
Input Max Allowable Undershoot (3.3V LVTTL)
V
IMAU
-0.6
V
Output Max Allowable Overshoot (3.3V LVTTL)
V
OMAO
+3.9
V
Output Max Allowable Undershoot (3.3V LVTTL)
V
OMAU3
-0.6
V
Case Temperature:
333MHz, 400MHz, and 533MHz parts in any package
667MHz parts in the E-PBGA package
667MHz parts in the TE-PBGA package.
T
C
-40
-40
-40
+100
+85
+95
°
C
Notes:
1. PCI drivers meet PCI specifications.
2. SV
REF
= SV
DD
/2
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440EP. See “Absolute Maximum Ratings” on page 59.
Table 8. Recommended DC Operating Conditions (Sheet 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes