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參數(shù)資料
| 型號： | PPC440EP |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Power PC 440EP Embedded Processor |
| 中文描述： | 440EP的Power PC嵌入式處理器 |
| 文件頁數(shù)： | 54/84頁 |
| 文件大?。?/td> | 541K |
| 代理商： | PPC440EP |
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54
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Revision 1.26 – April 25, 2007
Data Sheet
External Master Peripheral Interface
BusReq
Bus Request. Used when the PPC440EP needs to regain
control of peripheral interface from an external master.
O
Multiplex
ExtAck
External Acknowledgement. Used by the PPC440EP to
indicate that a data transfer occurred.
O
Multiplex
ExtReq
External Request. Used by an external master to indicate it is
prepared to transfer data.
I
Multiplex
1, 4
ExtReset
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
O
3.3V LVTTL
HoldAck
Hold Acknowledge. Used by the PPC440EP to transfer
ownership of peripheral bus to an external master.
O
Multiplex
HoldReq
Hold Request. Used by an external master to request
ownership of the peripheral bus.
I
Multiplex
1, 5
HoldPri
Hold Primary. Used by an external master to indicate the
priority of a given external master tenure.
I
Multiplex
PerClk
Peripheral Clock. Used by an external master and by
synchronous peripheral slaves.
O
3.3V LVTTL
UART Peripheral Interface
UARTSerClk
Serial clock input that provides an alternative to the internally
generated serial clock. Used in cases where the allowable
internally generated clock rates are not satisfactory.
I
3.3V LVTTL
1, 4
UARTn_Rx
UART Receive data.
I
3.3V LVTTL
1, 4
UARTn_Tx
UART Transmit data.
O
3.3V LVTTL
4
UARTn_DCD
UART Data Carrier Detect.
I
3.3V LVTTL
6
UARTn_DSR
UART Data Set Ready.
I
3.3V LVTTL
6
UARTn_CTS
UART Clear To Send.
I
3.3V LVTTL
1, 4, 6
UARTn_DTR
UART Data Terminal Ready.
O
3.3V LVTTL
4
UARTn_RTS
UART Request To Send.
O
3.3V LVTTL
4
UARTn_RI
UART Ring Indicator.
I
3.3V LVTTL
1, 4
IIC Peripheral Interface
IIC0SClk
IIC0 Serial Clock.
I/O
3.3V LVTTL
1, 2
IIC0SData
IIC0 Serial Data.
I/O
3.3V LVTTL
1, 2
IIC1SClk
IIC1 Serial Clock.
I/O
Multiplex
IIC1SData
IIC1 Serial Data.
I/O
Multiplex
Table 6. Signal Functional Description (Sheet 5 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400CZ | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400E | Power PC 440GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EP-3BB533C | 制造商:AppliedMicro 功能描述: |
| PPC440EP-3BC400C | 制造商:AMCC 功能描述:MPU 440EP RISC 16BIT 0.13UM 400MHZ 3.3V 456PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC440EP-3BC400C APD BIAS CTRL/MONITR |
| PPC440EP-3BC533C | 制造商:AppliedMicro 功能描述:MPU 440EP RISC 16-Bit 0.13um 533MHz 3.3V 456-Pin EBGA Tray |
| PPC440EP-3JA333CZ | 制造商:AppliedMicro 功能描述: |
| PPC440EP-3JA400C | 制造商:AppliedMicro 功能描述: |
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