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參數(shù)資料
| 型號： | PPC440EP |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Power PC 440EP Embedded Processor |
| 中文描述： | 440EP的Power PC嵌入式處理器 |
| 文件頁數(shù)： | 57/84頁 |
| 文件大?。?/td> | 541K |
| 代理商： | PPC440EP |
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AMCC Proprietary
57
440EP – PPC440EP Embedded Processor
Data Sheet
Revision 1.26 – April 25, 2007
System Interface
SysClk
Main system clock input.
Clock
3.3V tolerant
2.5V CMOS
SysErr
Set to 1 when a machine check is generated.
O
3.3V tolerant
2.5V CMOS
SysReset
Main system reset. External logic can drive this bidirectional
pin low (minimum of 16 cycles) to initiate a system reset. A
system reset can also be initiated by software. Implemented as
an open-drain output (two states; 0 or open circuit).
I/O
3.3V tolerant
2.5V CMOS
1, 2
Halt
Halt from external debugger.
I
3.3V LVTTL
1, 4
TmrClk
Processor timer external input clock.
I
3.3V tolerant
2.5V CMOS
GPIO00:63
General purpose I/O 0 through 63. To access these functions,
software must set DCR register bits.
I/O
Multiplex
TestEn
Test Enable.
I
3.3V LVTTL
3
RcvrInh
Receiver Inhibit. Active only when TestEn is active. Used for
manufacturing test only.
I
Multiplex
ModeCtrl
Mode Control. Active only when TestEn is active. Used for
manufacturing test only.
I
Multiplex
LeakTest
Leakage Test. Active only when TestEn is active. Used for
manufacturing test only.
I
Multiplex
RefEn
Reference Enable. Active only when TestEn is active. Used for
manufacturing test only.
I
Multiplex
DrvrInh1
Driver Inhibit. Active only when TestEn is active. Used for
manufacturing test only.
I
3.3V tolerant
2.5V CMOS
DrvrInh2
Driver Inhibit. Active only when TestEn is active. Used for
manufacturing test only.
I
3.3V LVTTL
PSROOut
Module characterization and screening. Use for test purposes
only. Tie down as specified in Note 3 for normal operation.
O
Perf screen
ring osc
1, 3
Table 6. Signal Functional Description (Sheet 8 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關PDF資料 |
PDF描述 |
|---|---|
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400CZ | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400E | Power PC 440GP Embedded Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EP-3BB533C | 制造商:AppliedMicro 功能描述: |
| PPC440EP-3BC400C | 制造商:AMCC 功能描述:MPU 440EP RISC 16BIT 0.13UM 400MHZ 3.3V 456PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC440EP-3BC400C APD BIAS CTRL/MONITR |
| PPC440EP-3BC533C | 制造商:AppliedMicro 功能描述:MPU 440EP RISC 16-Bit 0.13um 533MHz 3.3V 456-Pin EBGA Tray |
| PPC440EP-3JA333CZ | 制造商:AppliedMicro 功能描述: |
| PPC440EP-3JA400C | 制造商:AppliedMicro 功能描述: |
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