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參數(shù)資料
| 型號： | PNX3000 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Analog front end for digital video processors |
| 中文描述： | 模擬前端數(shù)字視頻處理器 |
| 文件頁數(shù)： | 38/51頁 |
| 文件大?。?/td> | 285K |
| 代理商： | PNX3000 |
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2004 Oct 04
38
Philips Semiconductors
Preliminary specification
Analog front end for digital video
processors
PNX3000
d) ThemeasurementsmustbecarriedoutwiththeSiemensSAWfiltersG3962forvision IFandG9350forsound IF.
Input level for sound IF 10 mV (RMS) with 27 kHz deviation
e) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filter
PC/SC ratio. This PC/SC ratio is necessary to achieve the S/N
W
values as indicated.
20. The demodulated AM sound signal can be made available in the analog domain on LINE or SCART audio outputs
by selecting AM internal (bus bit AMX = 0).
21. The frequency range of the 2nd SIF channel is limited by the 2nd SIF anti-alias filter. If a 10.7 MHz FM radio IF signal
is supplied to the external 2nd SIF input; an external 10.7 MHz bandpass filter must be used; and the internal
anti-alias filter must be bypassed by setting bus bit SLPM = 1.
22. The cascade of sound trap and group delay correction filter compensates for the group delay pre-distortion of the BG
standard, curve A (see “Rec. ITU-R BT.470-4”). The indicated values are the difference between the group delay at
4.43 MHz and the group delay at 10 kHz.
23. The digitized U and V signals have the following polarity: U = +(B
Y) and V = +(R
Y).
24. The S/N ratio is defined as the ratio of the full scale black-to-white amplitude to the black level noise voltage
(RMS value).
25. The S/N ratio is defined as the ratio of the full scale peak-to-peak signal amplitude to the zero signal noise voltage
(RMS value).
26. The video ADC is specified as a stand-alone circuit. Distortion and noise of the video switch and anti-alias filters is
not included.
27. The gain of the microphone amplifiers can be switched between low (17 dB) and high (35 dB). The low gain can be
used for microphones with a sensitivity between 5 mV (RMS) and 40 mV (RMS) at 94 dB SPL. The high gain can be
used for microphones with a sensitivity of less than 5 mV (RMS) at 94 dB SPL.
28. If the audio supply voltage is 8 V; the 5 V full scale reference voltage for the audio A to D converters at pin 91
(VAADCP) is generated by the IC itself, using the internal bandgap reference. This gives the best power supply
rejection ratio for the digital audio outputs. If the audio supply voltage is 5 V; pin 91 must be connected to the external
5 V supply. This results in a reduced power supply rejection ratio for the digital audio outputs.
29. Signals HV_PRIM and HV_SEC must be generated by the digital video processor using a 13.5 MHz clock. Where
pulse widths are specified in clock pulses, a 13.5 MHz clock is assumed (1 clock pulse is 74.1 ns). To enable
detection of the vertical blanking interval, a larger pulse width is used for a number of lines during the vertical blanking
period; see Figs 9 and 10.
30. Most timing parameters in this section are expressed in number of clock cycles, abbreviated as ck.
31. The east-west drive circuit is a voltage to current converter circuit, that requires an external conversion resistor. The
open drain output transistor can only sink current. The relation between input voltage and output current is as follows:
V
4
R
ew
×
where R
ew
is the external conversion resistor. The voltage across the external conversion resistor is
equal to V
i
/4. The voltage at output pin EWIOUT must not be lower than V
i
/4 + 0.25 V. The output current must not
be larger than 1.2 mA.
32. The switching levels of pins SDA and SCL are compatible with an external signal amplitude of 3.3 V and 5 V.
33. The IRQ output is an open-drain output; active LOW. The pin IRQ must be loaded with a pull-up resistor.
I
o
-------------------
=
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相關代理商/技術參數(shù) |
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