參數(shù)資料
型號(hào)： PNX3000
廠商： NXP Semiconductors N.V.
英文描述： Analog front end for digital video processors
中文描述： 模擬前端數(shù)字視頻處理器
文件頁(yè)數(shù)： 13/51頁(yè)
文件大?。?/td> 285K
代理商： PNX3000
2004 Oct 04
13
Philips Semiconductors
Preliminary specification
Analog front end for digital video
processors
PNX3000
Table 1
Overview of anti-alias filter bandwidths and video signal sample rates.
SIGNAL TYPE
SIGNAL
COMPONENT
SIGNAL BAND
1.0 dB (MHz)
8
8
8
8
4
4
16
8
8
10
8
SIGNAL BAND
3.0 dB (MHz)
9
9
9
9
4.5
4.5
18
9
9
12
9
SAMPLE
FREQUENCY (MHz)
CVBS
YC
27
27
27
27
13.5
13.5
54
27
27
27
Y
C
Y
U
V
Y
U
V
YUV 1f
H
YUV 2f
H
DTV
2nd SIF
7.7
Audio source selectors and A to D converters
The PNX3000 contains two different audio source
selectors.Thefirstselectorselectswhichaudiosignalsare
routed to the audio ADCs for further processing in the
digital domain. The two microphone inputs are also
connected to this selector. The selector has two outputs, a
primary channel and a secondary channel. The primary
audio channel is used for one stereo signal. The
secondary audio channel can carry a second stereo
signal, or two microphone signals, or one mono signal and
one microphone signal or one mono signal and one
AM sound signal.
The second selector selects which audio signals are fed to
the analog audio outputs for SCART and line out. This
selector also has two stereo inputs for demodulated sound
signals coming from the digital video processor.
The gain from an external audio input to an analog output
is 1. A supply voltage of 5 V allows input and output
amplitudes of 1 V (RMS) full scale. The PNX3000 has
separate supply voltage pins for the audio selector circuit.
To allow for input and output amplitudes of 2 V (RMS) full
scale, as required for compliance with the SCART
specification, an audio supply voltage of 8 V must be used.
The audio ADCs are 1-bit sigma-delta converters that
operate at a clock frequency of 6.75 MHz. The audio
A to D clock is synchronous with the video A to D clock, so
that audio and video data can be sent over the same data
links. The effective audio sample rate is
f
ksample/s.
7.8
Microphone inputs
The IC has two microphone inputs. One microphone input
can be used for voice control of the TV set with the help of
an intelligent voice command decoder. The second input
can be used for connection of a microphone for Karaoke.
To allow the use of microphones with different sensitivities
the gain of each microphone amplifier is switchable
between two values via the I
2
C-bus.
7.9
Clock generation, timing circuitry and black
level clamping
The IC contains two PLL circuits that derive the sample
clock for the ADCs and the bit and word clocks for the data
links from an external reference frequency. The reference
frequency must be a stable frequency of either 13.5 MHz
or 27 MHz from a crystal oscillator. The internal reference
frequency is always 13.5 MHz. If the external frequency is
27 MHz a prescaler must be activated by bus bit FXT.
One PLL is used to multiply the 13.5 MHz reference
frequency to the 27 MHz and 54 MHz clock frequencies
that are needed for the video ADCs. A second PLL is used
to obtain the 297 MHz bit clock for the data link
transmitters.
A special timing circuit is used to generate the horizontal
and vertical timing pulses that are needed in the IF part,
and also for clamping the black level of the selected video
signals to a defined value at the output of the video ADCs.
The horizontal and vertical timing information of the
primary and secondary video channels must be supplied
by the digital video processor on pins HV_PRIM and
HV_SEC. The signal on these pins must consist of a
128
52.7
=
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