
Philips Semiconductors
PNX1300/01/02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION
A-54
Floating-point multiply
SYNTAX
[ IF r
guard
] fmul r
src1
r
src2
→
r
dest
FUNCTION
if
r
guard
then
r
dest
←
(float)r
src1
×
(float)r
src2
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ifmul
28
2
No
—
3
2, 3
DESCRIPTION
The
fmul
operation computes the product r
src1
×
r
src2
and stores the result into r
dest
. All values are in IEEE single-
precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is
denormalized, zero is substituted for the argument before computing the product, and the IFZ flag in the PCSW is set.
If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
fmul
causes an
IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw
operation. The update of the PCSW exception flags occurs at the same time as r
dest
is written. If any other floating-
point compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR of
all simultaneous updates ORed with the existing PCSW value for that exception flag.
The
fmulflags
operation computes the exception flags that would result from an individual
fmul
.
The
fmul
operation optionally takes a guard, specified in r
guard
. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of r
guard
is 1, r
dest
and the exception flags in PCSW are written;
otherwise, r
dest
is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r60 = 0xc0400000 (
–
3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (
–
3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e
–
38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e
–
38)
r41 = 0x3f000000 (0.5),
r80 = 0x00800000 (1.17549435e
–
38)
r42 = 0x7f800000 (+INF),
r43 = 0x0 (0.0)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e
–
39)
r82 = 0x00c00000 (1.763241526e
–
38),
r83 = 0x8080000 (
–
1.175494351e
–
38)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (
–
INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00800000 (1.763241526e
–
38)
fmul r60 r30
→
r90
r90
←
0xc0400000 (-3.0)
fmul r40 r60
→
r95
r95
←
0xc1100000 (-9.0)
IF r10 fmul r40 r80
→
r100
no change, since guard is false
IF r20 fmul r40 r80
→
r105
r105
←
0x1400000 (3.52648305e-38)
fmul r41 r80
→
r110
r110
←
0x0, OFZ, UNF, INX flags set
fmul r42 r43
→
r106
r106
←
0xffffffff (QNaN), INV flag set
fmul r40 r81
→
r111
r111
←
0, IFZ flag set
fmul r82 r83
→
r112
r112
←
0, UNF, INX flag set
fmul r84 r85
→
r113
r113
←
0xff800000 (-INF)
fmul r70 r70
→
r120
fmul r80 r80
→
r125
r120
←
0x7f800000, OVF INX flags set
r125
←
0, UNF, INX flag set
SEE ALSO
imul
umul
dspimul
dspidualmul
fmulflags
readpcsw
writepcsw
fmul