PNX1300/01/02/11 Data Book
Philips Semiconductors
8-6
PRELIMINARY SPECIFICATION
8.7
AUDIO IN OPERATION
Figure 8-5
,
Table 8-8
and
Table 8-9
describe the func-
tion of the control and status fields of the AI unit. To en-
sure compatibility with future devices, undefined bits in
MMIO registers should be ignored when read, and writ-
ten as
’
0
’
s.
The AI unit is reset by a PNX1300 hardware reset, or by
writing 0x80000000 to the AI_CTL register. Upon RE-
SET, capture is disabled (CAP_ENABLE = 0), and
buffer1 is the active buffer (BUF1_ACTIVE=1). A mini-
mum of 5 valid AI_SCK clock cycles is required to allow
internal AI circuitry to stabilize before enabling capture.
This can be accomplished by programming AI_FREQ
and AI_SERIAL and then delaying for the appropriate
time interval.
Programing of the AI_SERIAL MMIO register needs to
follow the following sequence order:
set AI_FREQ to ensure that a valid clock is gener-
ated (Only when AI is the master of the audio clock
system)
MMIO(AI_CTL) = 1 << 31; /* Software Reset */
MMIO(AI_SERIAL) = 1 << 31; /* sets serial-master
mode, starts AI_SCK */
MMIO(AI_SERIAL) = (1 << 31) | (SCKDIV value); /*
then set DIVIDER values */
The DSPCPU initiates capture by providing two equal
size empty buffers and putting their base address and
size in the BASE
and SIZE registers. Once two valid (lo-
cal memory) buffers are assigned, capture can be en-
abled by writing a
‘
1
’
to CAP_ENABLE. The AI unit hard-
ware now proceeds to fill buffer 1 with input samples.
Once buffer 1 fills up, BUF1_FULL is asserted, and cap-
ture continues without interruption in buffer 2. If
BUF1_INTEN is enabled, a SOURCE 11 interrupt re-
quest is generated.
Table 8-8. AI MMIO control fields
Field Name
Description
RESET
The AI logic is reset by writing a 0x80000000
to AI_CTL. This bit always reads as a
‘
0
’
.
See
Section 8.7,
“
Audio In Operation
”
for
details on software reset.
0
normal operation (RESET default)
1
diagnostic mode (see
Section 8.11,
“
Diagnostic Mode
”
)
0
participate in global power down
(RESET default)
1
refrain from participating in power down
Capture Enable flag. If 1, AI unit captures
samples and acts as DMA master to write
samples to local SDRAM. If
’
0
’
(RESET
default), AI unit is inactive.
Buffer 1 full Interrupt Enable. Default 0.
0
no interrupt
1
interrupt (SOURCE 11) if buffer 1 full
Buffer 2 full interrupt enable. Default 0
0
no interrupt
1
interrupt (SOURCE 11) if buffer 2 full
HBE Interrupt Enable. Default 0.
0
no interrupt
1
interrupt (SOURCE 11) if a highway
bandwidth error occurs.
Overrun Interrupt Enable. Default 0
0
no interrupt
1
interrupt (SOURCE 11) if an overrun
error occurs
Write a
’
1
’
to clear the BUF1_FULL flag and
remove any pending BUF1_FULL interrupt
request. This bit always reads as 0.
Write a
’
1
’
to clear the BUF2_FULL flag and
remove any pending BUF2_FULL interrupt
request. This bit always reads as 0.
Write a
’
1
’
to clear the HBE flag and
remove any pending HBE interrupt request.
This bit always reads as 0.
Write a
’
1
’
to clear the OVERRUN flag and
remove any pending OVERRUN interrupt
request. This bit always reads as 0.
DIAGMODE
SLEEPLESS
CAP_ENABLE
BUF1_INTEN
BUF2_INTEN
HBE_INTEN
OVR_INTEN
ACK1
ACK2
ACK_HBE
ACK_OVR
Table 8-9. AI MMIO status fields (read only)
Field Name
Description
BUF1_ACTIVE
If
‘
1
’
, buffer 1 will be used for the next
incoming sample. If
‘
0
’
, buffer 2 will receive
the next sample.
1 after RESET.
BUF1_FULL
If
‘
1
’
, buffer 1 is full. If BUF1_INTEN is also
‘
1
’
, an interrupt request (source 11) is
pending. BUF1_FULL is cleared by writing
a
‘
1
’
to ACK1, at which point the AI hard-
ware will assume that BASE1 and SIZE
describe a new empty buffer.
0 after RESET.
If
‘
1
’
, buffer 2 is full. If BUF2_INTEN is also
‘
1
’
, an interrupt request (source 11) is
pending. BUF2_FULL is cleared by writing
a
‘
1
’
to ACK2, at which point the AI hard-
ware will assume that BASE2 and SIZE
describe a new empty buffer.
0 after RESET.
Highway Bandwidth Error. Condition raised
when the 64-byte internal AI buffer is not
yet written to SDRAM when a new input
sample arrives. Indicates insufficient allo-
cation of PNX1300 highway bandwidth for
the audio sampling rate/mode. Refer to
Chapter 20,
“
Arbiter.
”
0 after RESET.
OVERRUN error occurred, i.e. the CPU did
not provide an empty buffer in time, and 1
or more samples were lost. If OVR_INTEN
is also 1, an interrupt request (source 11)
is pending. The OVERRUN flag can ONLY
be cleared by writing a
‘
1
’
to ACK_OVR.
0 after RESET.
BUF2_FULL
HBE
OVERRUN
Table 8-9. AI MMIO status fields (read only)
Field Name
Description