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| 型號： | PM908E624ACDWBR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| 封裝： | PLASTIC, SOIC-54 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 718K |
| 代理商： | PM908E624ACDWBR2 |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
908E624
13
DYNAMIC ELECTRICAL CHARACTERISTICS
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the MCU chip.
Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
PHYSICAL LAYER
Driver Characteristics for Normal Slew Rate (Note 15)
Dominant Propagation Delay Tx to LIN (Measurement Threshold 58.1% VSUP)tDOM-min
––
50
s
Dominant Propagation Delay Tx to LIN (Measurement Threshold 28.4% VSUP)tDOM-max
––
50
s
Recessive Propagation Delay Tx to LIN (Measurement Threshold 42.2% VSUP)tREC-min
––
50
s
Recessive Propagation Delay Tx to LIN (Measurement Threshold 74.4% VSUP)tREC-max
––
50
s
Propagation Delay Symmetry: tDOM-min - tREC-max
dt1
-10.44
–
8.12
s
Propagation Delay Symmetry: tDOM-max - tREC-min
dt2
-10.44
–
8.12
s
Driver Characteristics for Slow Slew Rate (Note 15)
Dominant Propagation Delay Tx to LIN (Measurement Threshold 61.1% VSUP)tDOM-min
––
100
s
Dominant Propagation Delay Tx to LIN (Measurement Threshold 25.1% VSUP)tDOM-max
––
100
s
Recessive Propagation Delay Tx to LIN (Measurement Threshold 38.9% VSUP)tREC-min
––
100
s
Recessive Propagation Delay Tx to LIN (Measurement Threshold 77.8% VSUP)tREC-max
––
100
s
Propagation Delay Symmetry: tDOM-min - tREC-max
dt1s
-21.88
–
17.44
s
Propagation Delay Symmetry: tDOM-max - tREC-min
dt2s
-21.88
–
17.44
s
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
SRFAST
–20
–
V/
s
Receiver Characteristics and Wake-Up Timings
Receiver Dominant Propagation Delay (Note 16)
trL
–3.5
6.0
s
Receiver Recessive Propagation Delay (Note 16)
trH
–3.5
6.0
s
Receiver Propagation Delay Symmetry
tr-Sym
-2.0
–
2.0
s
Bus Wake-Up Deglitcher
tpropWL
30
50
80
s
Bus Wake-Up Event Reported Note
twake
–20
–
s
HIGH-SIDE OUTPUTS HS1 AND HS2
Turn On Time Delay (Note 18)
tdon
––
10
s
Turn Off Time Delay (Note 18)
tdoff
––
10
s
Notes
15.
VSUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 k, 6.8 nF/660, 10 nf/500. Measurement thresholds: 50% of Tx signal to LIN signal
threshold defined at each parameter.
16.
Measured between LIN signal threshold VIL or VIH and 50% of Rx signal.
17.
twake is typically 2 internal clock cycles after LIN rising edge detected. Refer to “LIN Bus Wake-Up Behavior” figure. In SLEEP mode the VDD
rise time is strongly dependant upon the decoupling capacitor at VDD terminal.
18.
Delay between turn on or turn off command and high-side on or high-side off, excluding rise or fall time due to external load.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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