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| 型號： | PM908E624ACDWBR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| 封裝： | PLASTIC, SOIC-54 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 718K |
| 代理商： | PM908E624ACDWBR2 |
908E624
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
20
ANALOG DIE DESCRIPTION
General Description
The 908E624 analog die is an integrated circuit dedicated to
automotive applications. It includes the following functions:
One fully protected voltage regulator with 50 mA total
output current capability available at the VDD terminal
Voltage reset function
Configurable window watchdog function
Interrupt output report fault or wake-up
Wake-up from Lx wake input and LIN bus
LIN physical interface
Two 150 mA high-side protected switches PWM capable
for relay or lamp drive
One 50 mA high-side protected switch for Hall-effect
sensor, etc.
Operational amplifier
Operation Modes
Operating modes are controlled by the MODE1 and MODE2
bits in the SPI register. Three modes are available: Normal,
STOP, and SLEEP. Operation modes are described in Table 1.
To safely enter SLEEP or STOP mode and to ensure that
these modes are not affected by noise issue during SPI
transmission, a dedicated sequence must be send twice:
Enter SLEEP Mode
Two identical SPI commands with:
D6 = 1, D7 = 1: for low-power (SLEEP or STOP) request.
D5: “1” for LIN pull-up disabled or “0” for pull-up enabled.
D1 = 0, D0 = 0: for SLEEP mode.
Enter STOP Mode
Two identical SPI commands with:
D6 = 1, D7 = 1: for low-power (SLEEP or STOP) request.
D5: “1” for LIN pull-up disabled or “0” for pull-up enabled.
D1 = 0, D0 = 1: for STOP mode.
SLEEP or STOP mode is entered after the second SPI
command.
Interrupts
The IRQB_A terminal is used to report a fault to the MCU. An
interrupt pulse is generated in case of any of the following: VDD
regulator temperature pre-warning, high-side switch 1, 2, or 3
thermal shutdown, VSUP overvoltage (19.25 V typ), and VSUP
undervoltage (6.0 V typ).
This terminal reports to the MCU the L1, L2, or LIN bus wake-
up event when the product is in STOP mode.
After an Interrupt or a wake-up, the register bit INT SOURCE
is set, indicating the source of the event. The SPI data register
will be transferred once.
High-Side Outputs
High-Side Output Terminals HS1 and HS2
These are two high-side switches to drive load such as
relays or lamps. They are protected against over current and
over temperature and include internal clamp circuitry for
inductive load drive. Control is done through SPI. PWM
capability is offered through the PWMIN input.
Table 1. Operation Modes
Mode
Reset
Normal
Request and
Normal
STOP
SLEEP
Voltage
Regulator
VDD on
VDD on.
Limited
current
capability
VDD off. Set
to 5.0 V
after wake-
up to enter
Normal
request
Wake-Up
Capabilities
N/A
LIN, state
change on
Lx inputs,
rising edge
on SSB
LIN, state
change on
Lx inputs,
rising edge
on SSB
Reset
Terminal
(RSTB_A)
Low
(1.0 ms)
after VDD
high
Normally
high. Active
low if VDD
undervoltage
occurs or if
WD fail (if WD
is enabled
Normally
high. Active
low if VDD
undervoltage
occurs
Low. Go to
high after
walk-up and
VDD within
specification
Watchdog
Not
running
Running if
enabled.
Period
selected by
resistor at
WDCONF
terminal. WD
cleared by
MODE1/
MODE2 bits
Not running
HS1, HS2,
HS3
OFF
ON or OFF
OFF
LIN
Recessive
only
Tx/Rx
Recessive
state with
wake
capability
Recessive
state with
wake
capability
Table 1. Operation Modes (continued)
Mode
Reset
Normal
Request and
Normal
STOP
SLEEP
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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